Pentium 4 and IA-32 ISA

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Pentium 4 and IA-32 ISA
Kyungseok Kim
Nov. 3, 2006
ELEC 5200/6200 Computer Architecture and Design,
Fall 2006 Lectured by Dr. V. Agrawal
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IA-32 ISA (CISC)

• The term means Intel Architecture, 32-bit
  (sometimes called i386)
• Instruction Set Architecture of Intels most
  successful microprocessors, called x86-32
• 32-bit extension of the original Intel x86
  processor architecture, 16-bit
• 64-bit architecture IA-64, Itanium Architecture
• IA-32 expanded by AMD in 2003 to support natively
  64-bit, AMD64 (AMD K8 family)
• IA-32e (NetBurst family, Intel Pentium4 and
  Xeon),
• later called EM64T
• AMD64 and EM64T are backwards compatible with
  32-bit code without any performance loss

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Two Memory Management

• Real Mode
• -8086, 8088 in DOS
• -Addressing only the first 1MB of memory
• -Segment address Offset address
• -Segment address
• The beginning address of any 64KB memory
  segment
• -Offset address
• Select any location within the 64KB Memory
  segment

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Two Memory Management

• Protected Mode
• - 80286 and above in Windows, Linux and others
• - Allows the access to data and programs located
  above the first 1MB of memory
• - Descriptor decides the memory segments
  location, length, and access rights.

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Registers

• Very small number of general purpose registers
• (approx. 4 integer plus 8 FP, versus 3232
  typical RISC)
• Small number of registers makes spilling more
  frequent
• Advanced compiler techniques increase register
  pressure.
• Partial specialization of the registers makes
  effective compiler scheduling difficult.

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IA-32 Instructions, since mid-80s

• Classic CISC set derived from extended
  accumulator architecture
• Improved orthogonality in the 32-bit extensions
  (80386)
• Added FP capabilities previously on a coprocessor
  (80486)
• Added MultiMedia Extensions MMX as SIMD
  (single-instruction multiple-data) integer
  instructions (Pentium II)
• Added Streaming SIMD Extension SSE, most notably
  consisting of SIMD FP instructions (Pentium III)
• Added SSE2, essentially extension of MMXSSE to
  128 bits (Pentium 4)

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Instruction Encoding

• One instr. Coded on 1 to 17 bytes in original
  IA-32
• Several types of modifiers/ prefixes
• Two combinations of constants of variable length
• -Immediate and Displacement
• -8, 16, and 32-bit

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Intel Processors
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Pentium 4

• Seventh-Generation x86 architecture by Intel
  (NetBurst)
• Very deep instruction pipeline with the intention
  of scaling to very high frequencies
• The SSE2 instruction set for faster SIMD integer,
  and 64bit floating point
• Later Pentium 4 models introduced new
  technological advances such as Hyper-Threading, a
  feature to make one physical CPU appear as two
  logical and virtual CPUs.

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NetBurst Architecture
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Conclusion

• IA-32 is the oldest important ISA around
• It is not absolutely fixed but constantly
  evolving with many new add-on
• (MMX, SSE, SSE2, etc.)
• Intel has managed to continue pushing the
  performance by adapting to its CICS nature the
  techniques developed to speed-up newer RISC
  Processors
• IA-32 is evolving toward 64 bits

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Reference

• http//www.intel.com
• http//lapwww.epfl.ch/courses/archord2/
• http//en.wikipedia.org/wiki/IA-32
• http//www.cs.pitt.edu/cho/cs2410/currentsemester
  /handouts/