A history of PC buses

1
A history of PC buses

• From ISA to PCI Express

2
ISA (Industry Standard Architecture) - 1981

• Originated in the original IBM PC (8-bit / 4.77
  MHz 4 MB/s).
• The ISA standard is based on PC/AT (16-bit / 8
  MHz 16 MB/s) 1984
• 62 pins (8-bit PC ISA) or 98 pins (16-bit PC/AT
  ISA).
• The ISA bus supported 1MB (PC/XT) / 16 MB (PC/AT)
  Memory and 64K I/O address spaces.
• Lacked bandwidth for graphical user interfaces
  (MS Windows).
• VL Bus (VESA Local Bus) gave some bandwidth
  respite on newer PC motherboards but was married
  to the 486/33 CPU bus.
• VL Bus no longer worked when Pentium came out (60
  MHz ) due to different CPU bus protocol.
• Later, IBM created MCA as future-proof,
  CPU-independent alternative.

3
ISA (Industry Standard Architecture) 1981
(cont.)

• 8-bit and 16-bit ISA slots

4
ISA (Industry Standard Architecture) 1981
(cont.)

• 16-bit ISA slot signals (PC/AT)

5
MCA (Micro Channel Architecture) 1987

• Created by IBM to address deficiencies of the ISA
  bus (CPU-dependence and lack of performance).
• Used by IBM PS/2 computers.
• 16/32 bits, 10 MHz, 20/40 MB/s
• Software-based configuration (i.e. no IRQ, DMA
  jumpers).
• Was not an open standard so never caught on with
  PC manufacturers.
• Not backwards compatible with existing ISA
  expansion cards.
• Was used by advanced server platforms due to high
  overall performance.

6
MCA (Micro Channel Architecture) 1987 (cont.)

• 32-bit MCA slots. Connector later reused by PCI.

7
EISA (Extended Industry Standard Architecture) -
1988

• Created by 3rd-party PC clone vendors.
• 32-bit / 8 MHz 32 MB/s.
• Software-based configuration (i.e. no IRQ, DMA
  jumpers).
• EISA slots accepted ISA cards but EISA cards
  would not work in ISA slots.
• Was never popular because ISA VLB carried the
  PC platform until PCI came along.
• Did see use in higher-performance server systems.

8
EISA (Extended Industry Standard Architecture)
1988 (cont.)

• EISA slots Accepts ISA cards too.

9
EISA (Extended Industry Standard Architecture)
1988 (cont.)

• EISA card Does not fit in ISA slot.

10
VLB (VESA Local Bus ) 1992

• 32-bit, 33 MHz 133 MB/s.
• Created by Video Electronics Standards
  Association (VESA) for attaching high-performance
  graphics cards to ISA, and later PCI,
  motherboards.
• Custom slot that extends the 16-bit ISA slot (see
  next slide).
• Directly tied to the 486/33 memory bus Doomed
  for other CPUs due to different CPU memory bus
  protocol.
• The CPU memory bus only allowed one or two VLB
  card loads (due to loading and SI issues).
• Difficult implementation, especially for 40/50
  MHz 486 versions (instability common).
• 486DX2-66 and -100 used a 33 MHz front-side bus
  (x2/x3 internal clock) so compatible with VLB.

11
VLB (VESA Local Bus ) 1992 (cont.)

• 32-bit VLB slot on ISA motherboard.

12
VLB (VESA Local Bus ) 1992 (cont.)

• 32-bit VLB Graphics Card

13
PCI (Peripheral Component Interconnect) 1992

• Created by Intel (later PCI-SIG) to bring
  together best ideas from prior bus architectures.
• 32-bit, 33 MHz 133 MB/s
• Also supported 64-bit (while not commonly
  implemented) 266 MB/s
• Full plug-and-play (cards report Memory, IRQ, I/O
  requirements device drivers and operating
  system make sure the cards get the resources they
  need and that no resource clashes occur).
• Growing used PCI bandwidth eventually
  necessitated separate AGP graphics card bus.

14
PCI (Peripheral Component Interconnect) 1992
(cont.)

• 4x32-bit PCI slots 4x16-bit ISA slots.

15
PCI (Peripheral Component Interconnect) 1992
(cont.)

• PCI bus now decoupled from CPU bus.

16
PCI (Peripheral Component Interconnect) 1992
(cont.)

• PCI Bus interface signals (32/64 bit data).

17
PCI (Peripheral Component Interconnect) 1992
(cont.)

• Configuration Space Registers PnP

18
PCI-X (Peripheral Component Interconnect -
Extended) - 1998

• 32/64-bit, 66/133/266/533 MHz (up to 4,266 MB/s).
• PCI-SIG (IBM, Compaq, HP). Note Intel wanted a
  better option.
• Improved protocol over PCI (Split-Response
  Transactions, MSI signals interrupts via memory
  writes in host PCI bridge rather than dedicated
  INTx interrupt lines.).
• Due to higher cost, normally only server PCs used
  64-bit PCI-X.
• Desktop systems migrated directly from PCI to PCI
  Express, bypassing PCI-X.
• Wide buses resulted in difficult length matching
  of the bus signals (in worst case, violating
  Tsu/Th).
• PCI-X reached practical frequency limit due to
  loading and skew of the wide buses
• The wide buses tied up most I/O pins on the
  chipsets, limiting overall chip functionality.

19
PCI-X (Peripheral Component Interconnect -
Extended) 1998 (cont.)
20
PCI-X (Peripheral Component Interconnect -
Extended) 1998 (cont.)

• Fast and wide buses result in Tsu/Th timing skew
  between signals within the buses.
• If the skew is too high, the interface will break!

21
PCI Express 2004

• Actually not a bus but a point-to-point link.
• High-speed bi-directional serial link (2.5 / 5.0
  / 8.0 Gbps per lane, 1 to 32 lanes).
• Clock 8b/10b encoded within serial data stream.
• Maintains software backwards compatibility of
  Configuration Space registers (Plug-and-Play).
• Also software backwards compatible with regards
  to I/O and Memory-mapped device registers.
• No length matching between lanes needed (separate
  lane-to-lane de-skew built into receiver).

22
PCI Express 2004 (cont.)

• PCI Express vs. PCI slots.

23
PCI Express 2004 (cont.)

• PCI Express bandwidth comparison.

24
PCI Express 2004 (cont.)

• PCI Express 1.0a/1.1 250 MB/s per lane (max 8
  GB/s for 32 Lanes) 2003/2005.
• PCI Express 2.0 500 MB/s per lane (max 16 GB/s
  for 32 Lanes) - 2007.
• PCI Express 3.0 800 MB/s per lane (max 26 GB/s
  for 32 Lanes) - 2010.
• PCI Express 4.0 Again doubling transfer rate?
  Expected to be released 2014/2015.
• Efficient and physically compact enables use for
  all platforms (mobile, desktop, server).
• No longer need for separate AGP graphics bus slot
  (lots of available bandwidth).

25
A history of PC buses

• This completes the overview of the legacy PC
  buses.
• For a continued description of the PCI Express
  bus architecture, see the presentation PCI
  Express 101.