Title: RTL Design Methodology
1Lecture 10 RTL Design Methodology Sorting
2Structure of a Typical Digital System
Data Inputs
Control Inputs
Control Signals
Datapath (Execution Unit)
Controller (Control Unit)
Status Signals
Data Outputs
Control Outputs
3Hardware Design with RTL VHDL
Interface
Pseudocode
Datapath
Controller
Block diagram
Block diagram
State diagram or ASM chart
VHDL code
VHDL code
VHDL code
4Steps of the Design Process
- Text description
- Interface
- Pseudocode
- Block diagram of the Datapath
- Interface with the division into the Datapath
- and the Controller
- ASM chart of the Controller
- RTL VHDL code
- Testbench
- Debugging
- Synthesis and implementation
- Experimental testing
5Steps of the Design ProcessPracticed in Class
- Text description
- Interface
- Pseudocode
- Block diagram of the Datapath
- Interface with the division into the Datapath
- and the Controller
- ASM chart of the Controller
- RTL VHDL code
- Testbench
- Debugging
- Synthesis and implementation
- Experimental testing
6Sorting Example
7Sorting - Required Interface
8Simulation results for the sort operation
(1)Loading the registers and starting sorting
9Simulation results for the sort operation
(2)Completing sorting and reading out registers
10Sorting - Example
During Sorting
After sorting
Before sorting
i0 i0 i0 i1 i1 i2 j1 j2 j3 j2 j3 j3
address
0 1 2 3
3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3
1 1 1 1 2 2 3 4
Legend
position of memory indexed by i
position of memory indexed by j
j
i
11Pseudocode
- wait for s1
- for i0 to k-2 do
- A Mi
- for ji1 to k-1 do
- B Mj
- if A gt B then
- Mi B
- Mj A
- A Mi
- end if
- end for
- end for
- Done
- wait for s0
- go to the beginning