Code Generation, Machine Dependent Compiler Features Intermediate Form Of The Program, MachineDepend

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Compilers

• Code Generation
• MACHINE - DEPENDENT CODE
  OPTIMIZATION
• Machine Independent Compiler Features
• MACHINE - INDEPENDENT CODE
• OPTIMIZATION

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• GENERATION OF OBJECT
• CODE
• Code generation phase is after the syntax
  phase.
• Semantic routines are called when the
  parser recognizes a portion of the source program
  according to some rule of the grammar.
• Simple scheme of a compiler Semantic routines
  generate object code directly.
• Some complex compilers generate an intermediate
  form of the program.

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The code generation routines that is
discussed are designed for the use
with the grammar in fig
The list of simplified Pascal grammar is shown in
fig. 1. lt prog gt PROGRAM lt program gt VAR
ltdec - list gt begin lt stmt -
list gt end. 2.    ltprog - namegt id 3.    lt
dec - list gt lt dec gt lt dec - list gt
4.    lt dec gt lt id - list gt lt type gt
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5.    lt type gt integer 6.    lt id - list gt
id lt id - list gt , id
7.    ltstmt - list gt lt stmt gt ltstmt - list gt
lt stmt gt 8.    lt stmt gt ltassigngt ltread gt
ltwritegt ltforgt 9.    lt assign gt id
lt exp gt 10.  ltexpgt lttermgtltexpgtlttermgt
ltexpgt - lttermgt 11.  lttermgtltfactorgtlttermgtltfacto
rgtlttermgtDIV ltfactorgt 12.  lt factorgt id
int (lt exp gt) 13.  lt READgt READ ( lt id -
list gt) 14.  lt write gt WRITE ( lt id - list
gt) 15.   lt for gt FOR lt idex - exp gt Do lt
body gt
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Note This grammar is used for code generations
to emphasize the point
that code generation techniques need not be
associated with any particular parsing method.
The code generation is for the SIC/XE machine.
The code generation routines use two data
structure (1) A List (2) A Stack Listcount
A variable Listcount is used to keep a count of
the number of items currently in the list.
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The code generation routine make use of token
specifiers and are denoted by S(token) .
Example id S (id) name of the
identifier int S (int) value of the integer,
100 The code generation routines create
segments of object code for the compiled program.
A symbolic representation is given to
these codes using SIC assembler language.
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LOCCTR It is a Location counter which is updated
to reflect the next variable
address in the compiled program (exactly as it is
in an assembler).
Application Process to READ Statement

The parser tree for Read statement can be
generated with many different parsing methods.
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In an operator precedence parse, the recognition
occurs when a sub-string of the input is reduced
to some non-terminal ltNigt.
In a recursive-descent parse, the recognition
occurs when a procedure returns to its caller,
indicating success.
Thus the parser first recognizes the id VALUE as
an ltid-listgt, and then recognizes the complete
statement as a lt read gt.
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The symbolic representation of the object code to
be generated for the READ statement is as shown.
JSUB XREAD WORD
1 WORD VALUE
This code consists of a call to a statement
XREAD, which world be a part of a standard
library associated with the compiler. The
subroutine of any program that wants to perform a
READ operation can call XREAD.
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The parameter list for XREAD is defined
immediately after the JSUB that calls it. The
first word is the number of variables that will
be assigned values by the READ.
The following word gives the addresses of these
variables. Routines that might be used to
accomplish the above code generation. lt id -
list gt id add S (id)
to list add 1 to Listcount
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lt id - list gt lt id - list gt, id
add S (id) to list
add 1 to LC ListCount
These two statements correspond to alternative
structure for lt id - list gt, that is ltid-list gt
id lt id - list gt, id. In either case,
the token specifier S(id) for a new identifier
being added to the ltid-listgt is inserted into the
list used by the code-generation routines, and
Listcount is updated in incrementing.
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lt read gt READ (lt id - list gt)
generate JSUB XREAD record
external reference to XREAD generate
WORD Listcount for each item on list
do begin remove S (ITEM) from
list generate WORD S (ITEM) end
List _count 0
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Code-generation Process for the
Assignment Statement
Example VARIANCESUMSQ DIV 100 - MEAN
MEAN
Solution
The parser tree for this statement is shown in
fig. Most of the work of parsing involves the
analysis of the ltexpgt on the right had side of
the " " statement.
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Parser Tree
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A code-generation routine is called for each
portion of the statement is recognized.
Example For a rule lttermgt1 lttermgt 2
ltfactorgt a code is to be generated. The
subscripts are used to distinguish between the
two occurrences of lttermgt . The code-generation
routines perform all arithmetic operations using
register A. Before multiplication one of the
operand lttermgt2 must be located in A-register.
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The results after multiplication,
lttermgt2 ltfactorgt will be left in register A.
So we need to keep track of the result left in
register A by each segment of code that is
generated. This is accomplished by extending
the token-specifier idea to non-terminal nodes of
the parse tree. The node specifier S(lttermgt1)
would be set to rA. This indicates that the
result of this computation is in register A.

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The variable REGA is used to indicate
the highest level node of the parse tree whose
value is left in register A by the code generated
so far.
1.          lt assign gt id ltexpgt GETA
(lt exp gt) generate STA S(id) REGA
null The code generation routine for ltassigngt
consists of bringing the value to be assigned
into register A (using GETA). The STA instruction
is generated to store the value in A register.
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Note that REGA is then set to null because the
code for the statement has been completely
generated, and any intermediate results are no
longer needed.
The following rules do not require the generation
of any machine instructions since no computation
or data movement is involved. The code generation
routines for these rules simply set the node
specifier of the higher-level node to reflect the
location of the corresponding value.
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2.     ltexpgt lt term gt S (lt exp gt)
S (lt term gt) if S (lt exp gt) rA
then REGA lt exp gt 3.     lt exp
gt1 lt exp gt2 lt term gt if
S(lt exp gt2) rA then generate
ADD S (lt term gt) else if S
(lt term gt) rA then
generate ADD S (lt exp gt2)
else
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begin GETA (lt EXP gt2) generate ADD S(lt
term gt) end S (lt exp gt1) rA
REGA lt exp gt1 4. lt exp gt1 lt exp gt2
- lt term gt if S(lt exp gt2) rA then
generate SUB S (lt term gt)
else
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begin GETA (lt EXP gt2) generate SUB
S(lt term gt) end S (lt exp gt1) rA
REGA lt exp gt1 5. lt term gt lt factor
gt S (lt term gt) S (lt factor gt)
if S (lttermgt) rA then
REGA lt term gt
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6. lttermgt1 lttermgt2ltfactorgt if S (lt term
gt2) rA then generate MUL S
(ltfactorgt) else if S (lt factor gt) rA then
generate MUL S (lt term
gt2) else begin GETA (lt term
gt2) generate MUL S(lt factor
gt) end S (lt term gt1) rA
REGA lt term gt1
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7. lttermgt lttermgt2 DIV ltfactorgt if S (lt
term gt2) rA then generate DIV S
(lt factor gt) else begin GETA
(lt term gt2) generate DIV S (lt
factor gt) end S (lt term gt1) rA REGA
lt term gt1
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8. lt factor gt id S (lt factor gt) S (id)
9. lt factor gt int S (lt factor gt) S
(int) 10. lt factor gt lt exp gt S (lt factor
gt) S (lt exp gt) if S (lt factor gt) rA then
REGA lt factor gt
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The GETA procedure is shown  Procedure - GETA
(NODE) begin if REGA null then
generate LDA S (NODE) else if S
(NODE) ? rA then begin creates a new
looking variable Tempi generate STA
Tempi record forward reference to Tempi S
(REGA) Tempi Generate LDA S (NODE)
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end (if ? rA) S(NODE) rA REGA
NODE end GETA
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The code generated for the above is as
follows LDA SUMSQ DIV 100 STA TMP1
LDA MEAN MUL MEAN STA TMP2 LDA TMP1 SU
B TMP2 STA VARIABLE
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• Most of the times, the phases of a
  compiler are collected into a front-end
  and a back-end.
• The front-end comprises of those phases or at
  times also parts of the phases which depend on
  the source language and are independent of the
  target machine. These include
• lexical analysis,
• syntactic analysis,
• creation of symbol table,
• semantic analysis and
• generation of intermediate code.

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It also includes some amount of error handling
and code optimization that goes along with these
phases.

• The back-end generally includes those phases of
  the compiler which depend on the target machine.
• They do not depend on the source language, just
  the intermediate language.
• Backend includes
• code optimization,
• code generation along with error handling and
• symbol-table operations.

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Some compilers generate an explicit intermediate
representation of the source program after syntax
and semantic analysis.

• This intermediate representation of the source
  program can be thought of as a program for an
  abstract machine and should have two main
  properties viz.,
• It should be easy to produce
• 2. It should be easy to translate into the target
  program

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Let us consider the situation given in the slide
above. Suppose, we
have to write a complier for m languages targeted
for n machines. The obvious approach would be to
write mn compilers.
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HLL
High Level language
This diagram shows two compilers converting
higher level language to two different object
codes for two machines. It means that for a
language it is necessary to have as many
compilers as the number of machines.
Compilers
Object code for M1
Object code for M2
Example C language to Intel processor and
Motorola processor
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An intermediate language avoids most of the
problems.
It allows a logical separation between machine
independent and dependent phases and facilitates
optimization. All we have to do is to choose a
rich intermediate language that would bridge both
the source programs and the target programs. The
first three phases are called as the front end of
the compiler because they are machine independent.
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The code generation and related phase is called
as the back end.
The intermediate code generation is neither
consider to be the back end nor front end. Next
slide shows three languages producing a common
intermediate code. From the intermediate code the
object code for the two M/C are obtained. Hence
if we have Mnumber of languages and N object
code is to be obtained, the number of front and
back end that needs to be written is NM.
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• MACHINE - DEPENDENT
• CODE OPTIMIZATION
•  There are several different possibilities for
  performing machine-dependent code optimization .
• Assignment and use of registers
• Divide the problem into basic blocks.
• Rearrangement of machine instruction to
  improve efficiency of execution

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The intermediate form that is discussed here
represents the executable instruction of the
program with a sequence of quadruples. Each
quadruples of the form
Operation, OP1, OP2, result. Where Operation - is
some function to be performed by the object
code OP1 OP2 - are the operands for the
operation and
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Result - designation when the resulting
value is to be placed. Example 1 SUM SUM
VALUE could be represented as ,
SUM, Value, i1 , i1,
, SUM The entry i1, designates an
intermediate result (SUM VALUE) the second
quadruple assigns the value of this intermediate
result to SUM. Assignment is treated as a
separate operation ( ).
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Example 2 VARIANCE SUMSQ DIV 100 - MEAN
MEAN DIV, SUMSQ, 100, i1
, MEAN, MEAN, i2
- , i1, i2, i3
, i3,
VARIABLE Note Quadruples appears in the order
in which the corresponding object code
instructions are to be executed. This greatly
simplifies the task of analyzing the code for
purposes of optimization. It is also easy to
translate into machine instructions.
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Example 3 For the program shown below write the
quadruples.
PROGRAM STATS VAR SUM, SUMSQ, I, VALUE, MEAN,
VARIANCE INTEGER BEGIN SUM 0
SUMSQ 0
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FOR I 1 to 100 DO
BEGIN READ (VALUE) SUM SUM
VALUE SUMSQ SUMSQ VALUE VALUE
END MEAN SUM DIV 100 VARIANCE
SUMSQ DIV 100 - MEAN MEAN WRITE
(MEAN, VARIANCE) END.
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Solution Line Operation OP 1 OP 2
Result Pascal Statement
1. 0
SUM SUM 0 2. 0
SUMSQ SUMSQ 0 3.
1 I FOR I 1 to 100
4. JGT I 100 (15)
5. CALL XREAD READ
(VALUE) 6. PARA VALUE
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• 7. SUM VALUE i1 SUM SUM
  VALUE
• 8. i1 SUM
• VALUE VALUE i2 SUMSQ SUMSQ
• 10. SUMSQ i2 i3
  VALUE VALUE
• 11. i3 SUMSQ
• 12. I 1 i4 End of FOR loop
• 13. i4 I

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14. J (4)
15. DIV SUM 100 i5 MEAN SUM DIV
100 16. i5 MEAN
17. DIV SUMSQ 100 i6 VARIANCE
18. MEAN MEAN i7 SUMSQ DIV
100 19. - i6 i7 i8 -
MEAN MEAN
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20. i8 VARIANCE
21.CALL XWRITE WRITE (MEAN,
VALIANCE 22. PARAM MEAN 23. PARAM VARIANCE
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• MACHINE - DEPENDENT CODE
• OPTIMIZATION
• There are several different possibilities for
  performing machine-dependent code optimization .
• Assignment and use of registers
• Registers is used as instruction operand.
• The number of registers available is limited.

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• Required to find the least used register
  to replace with new values when
  needed.
• Usually the existence of jump instructions
  creates difficulty in keeping track of registers
  contents.
• Divide the problem into basic blocks to tackle
  such problems.
• A basic block is a sequence of quadruples with
  one entry point, which is at the beginning of the
  block, one exit point, which is at the end of the
  block, and no jumps within the blocks.

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CALL operation is usually considered
to begin a new basic block.
When control passes from one block to another,
all values currently held in registers are saved
in temporary variables. For example 3, the
quadruples can be divided into five blocks. They
are Block -- A Quadruples 1 - 3
Block -- B Quadruples 4
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Block -- C Quadruples 5 - 14 Block --
D Quadruples 15 - 20 Block -- E Quadruples
21 - 23
Fig. shows the basic blocks of the flow group for
the quadruples. An arrow from one block to
another indicates that control can pass directly
from one quadruple to another.
This kind of representation is called a flow
group.
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• Rearranging quadruples before
• machine code generation
• Example 1) DIV SUMSQ 100 i1
• 2) MEAN MEAN i2
• 3) - i1 i2 i3
• 4) i3 VARIANCE

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LDA SUMSQ DIV 100 STA i1 LDA MEAN
MUL MEAN STA i2 LDA i1 SUB i2 STA i3 STA
Variance
shows a typical generation of machine code from
the quadruples using only a single register ie
Accumulator
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The optimizing compiler could
rearrange the quadruples so that
the second operand of
the subtraction is computed first. This results
in reducing two memory accesses.
MEAN MEAN i2 DIV SUMSQ
100 i1 - i1 i2
i3 i3 VARIANCE
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LDA MEAN MUL MEAN STA i1 LDA SUMSQ
DIV 100 SUB i1 STA VARIANCE
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• Characteristics and Instructions
• of Target Machine
• Special loop - control instructions or
  addressing modes can be used to create more
  efficient object code.
• High-level machine instructions can perform
  complicated functions such as calling procedure
  and manipulating data structures in a single
  operation.
• If multiple functional blocks can be used, the
  source code can be rearranged to use all the
  blocks or most of the blocks concurrently. This
  is possible if the result of one block does not
  depend on the result of the other.

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• Machine Independent Compiler
• Features
• Machine independent compilers describe the
  method for handling structured variables such as
  arrays.
• Problems involved in compiling a
  block-structured language indicate some possible
  solution.

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• STRUCTURED VARIABLES
• Structured variables discussed here are arrays,
  records, strings and sets.
• Arrays In Pascal array declaration
• Single dimension array
• A ARRAY 1 . . 10 OF INTEGER
• If each integer variable occupies one word of
  memory, then we require 10 words of memory to
  store this array.

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In general an array declaration is ARRAY
i .. u OF INTEGER Memory word allocated ( u
- i 1) words.
(ii) Two dimension array BARRAY 0 .. 3, 1
. . 3 OF INTEGER In this type of declaration
total word memory required is 0 to 3 4 1 to
3 3 4 x 3 12 word memory locations.
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In general ARRAY l1 .. u1, l2 . . u2. OF
INTEGER Requires ( u1 - l1 1) ( u2 -
l2 1) Memory words The data is stored in
memory in two different ways. They are
row-major and column major. All array elements
that have the same value of the first subscript
are stored in contiguous locations. This is
called row-major order. It is shown in fig.
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• Register Allocation
• Assign specific CPU registers for specific
  values.
• Code Generation must maintain information on
  which registers
• Are used for which purposes
• Are available for reuse
• Main objective
• ? Maximize the utilization of the CPU
  registers
• ? Minimize references to memory locations

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Possible uses for CPU registers
Values used many times in a program
Values that are computationally expensive
Importance ? Efficiency ? Speed
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Register Allocation Algorithm
Register Allocation Algorithm determines how many
registers will be needed to evaluate an
expression. It also determines the Sequence in
which sub-expressions should be evaluated to
minimize register use.
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• Construct a tree starting at the
  bottom nodes
• Assign each leaf node a weight of
• ? 1 if it is the left child
• ? 0 is it is the right child
• The weight of each parent node will be computed
  by the weights of the 2 children as follows
• ? If the 2 children have different weights, take
  the max.
• ? If the weights are the same, the parents
  weight is w

The number of CPU registers is determined by the
highest summed weight at any stage in the tree.
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RVCE
104

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
105

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
106

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
107

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
108

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
109

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
110

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
111

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
112

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
113

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
114

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
115

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
116

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
117

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
118

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RVCE
119

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RVCE
120
Code Generation, Machine Dependent Compiler
Features - Intermediate Form Of The Program,
Machine-Dependent Code Optimization, Machine
Independent Compiler Features - Structured
Variables, Machine Independent Code Optimization,
Storage Allocation, Block Structured Languages,
Compiler Design Options - Division Into Passes,
Interpreters, P-Code Compilers,
Compiler-Compilers.