Title: Chapter 3 System Buses
1Chapter 3System Buses
2Contents
- Computer Components
- Computer Function
- Interconnection Structures
- Bus Interconnection
- PCI
- Recommended Reading Web sites
3Program Concept
Computer components
- Hardwired systems are inflexible
- General purpose hardware can do different tasks,
given correct control signals - Instead of re-wiring, supply a new set of
- control signals
4What Is A Program?
Computer components
- A sequence of steps
- For each step, an arithmetic or logical
- operation is done
- For each operation, a different set of control
- signals is needed
5Function of Control Unit
Computer components
- For each operation a unique code is provided
- e.g. ADD, MOVE
- A hardware segment accepts the code and
- issues the control signals
- We have a computer!
6Hardware Software Approaches
Computer components
7Computer Components
Computer components
- Programming is now much easier
- To distinguish this new method of programming, a
sequence of codes or instruction is called
software - Instruction interpreter a module of
general-purpose arithmetic and logic functions
8Components
Computer components
- The process of connecting together the various
components in the desired configuration as a form
of programming - The resulting program is in the form of
hardware and is termed a hardwired program - The system accepts data and produces results
- For each step, a new set of control signals is
needed
9Components
Computer components
- The Control Unit and the Arithmetic and
- Logic Unit constitute the Central Processing
Unit - Data and instructions need to get into the
- system and results out
- Input/output
- Temporary storage of code and results is
- needed
- Main memory
10Computer ComponentsTop Level View
Computer components
11Basic Instruction Cycle
Computer function
12Instruction Fetch Execute
Computer function
- Program Counter (PC) holds address of next
instruction to fetch - Processor fetches instruction from memory
location pointed to by PC - Increment PC (Unless told otherwise)
- Instruction loaded into Instruction Register (IR)
- Instruction contains bits to act of processor
- Processor interprets instruction and performs
required actions
13Execute Cycle
Computer function
- Processor-memory
- data transfer between CPU and main memory
- Processor I/O
- Data transfer between CPU and I/O module
- Data processing
- Some arithmetic or logical operation on data
- Control
- Alteration of sequence of operations
- e.g. jump
- Combination of above
14Characteristics of A Hypothetical Machine
Computer function
15Example of Program Execution
Computer function
16Instruction Fetch Execute
Computer function
- With a more complex set of instruction, need
fewer cycle - Modern processor include instruction of
containing more than one address - Execution cycle for a particular instruction
involve more than one reference to memory
17Instruction Cycle State Diagram
Computer function
18Instruction Cycle State
Computer function
- Instruction address calculation (iac)
- Determine the address of the next instruction to
be executed - Instruction fetch (if)
- Read instruction from its memory location into
the processor - Instruction operation decoding (iod)
- Analyze instruction to determine type of
operation to be performed operands to be used - Operand address calculation (aoc)
- Determine the address of operand (If operation
involve reference to an operand in memory or I/O
module
19Instruction Cycle State
Computer function
- Operand fetch (of)
- Fetch the operand from memory or read it from I/O
- Data operation (do)
- Perform the operation indicated in the
instruction - Operand store (os)
- Write the result into memory or out to I/O
20Instruction Cycle State
Computer function
- Single Instruction specify an operation to be
performed on a vector of numbers or a string of
characters (on some machines)
21Interrupts
Computer function
- Mechanism by which other modules
- (e.g. I/O) may interrupt normal sequence of
- processing
- Interrupts provided to improve processing
efficiency - I/O program consists of three sections
- A sequence of instruction to prepare actual I/O
- operation
- The actual I/O command
- A sequence of instruction to complete operation
22Class of Interrupts
Computer function
- Program Generated by some condition
occurs as a result
of an instruction execution such as arithmetic
overflow division
by zero, attempt to execute an
illegal machine instruction, and
reference outside
a users allowed memory space - Timer Generated by a
timer within the processor. This
allows the operating system to
perform certain
functions on a regular basis - I/O Generated by
an I/O controller, to signal normal
completion of an operation or
to signal a variety
of error conditions - Hardware failure Generated by a failure such
as power failure or
memory parity error
23Interrupts The Instruction Cycle
Computer function
- Processor engaged in executing other instructions
while I/O operation is in progress (With
interrupts)
24Program Flow Control
Computer function
25Transfer of Control Via Interrupts
Computer function
- Processor and operation system are responsible
for suspending user program and resuming at the
same point
26Transfer of Control Via Interrupts
Computer function
27Interrupt Cycle
Computer function
- Added to instruction cycle
- Processor checks for interrupt
- Indicated by an interrupt signal
- If no interrupt, fetch next instruction
- If interrupt pending processor does
- Suspend execution of current program
- Save context
- Set PC to start address of interrupt handler
routine - Process interrupt
- Restore context and continue interrupted program
28Instruction Cycle With Interrupts
Computer function
29Program Timing Short I/O Wait
Computer function
- Less than time to complete execution of
instructions between write operations in user
program
30Program Timing Short I/O Wait
Computer function
31Program Timing Long I/O Wait
Computer function
- User program reaches second WRITE call before I/O
operation spawned by the first call is complete - User program is hung up at that point
32Program Timing Long I/O Wait
Computer function
- Gain efficiency because of time during which I/O
operation underway overlaps with execution of
user instructions
33Program Timing Long I/O Wait
Computer function
34Instruction Cycle (with Interrupts) - State
Diagram
Computer function
35Multiple Interrupts
Computer function
- Two approaches to dealing with multiple
interrupts - The first to disable interrupts while interrupt
being processed - Nice simple, Interrupts handled in strict
sequential order - Drawback Do not take into account relative
priority or time-critical needs
36Multiple Interrupts - Sequential
Computer function
37Multiple Interrupts - Sequential
Computer function
- Second to define priories for interrupts and to
allow interrupt of higher priority to cause
lower-priority interrupt handler to be itself
interrupted
38Multiple Interrupts - Nested
Computer function
39Multiple Interrupts
Computer function
- Disable interrupts
- Processor will ignore further interrupts whilst
processing one interrupt - Interrupts remain pending and are checked after
first interrupt has been processed - Interrupts handled in sequence as they occur
- Define priorities
- Low priority interrupts can be interrupted by
higher priority interrupts - When higher priority interrupt has been
processed, processor returns to previous interrupt
40Example Time Sequence of Multiple Interrupts
Computer function
41I/O Function
Computer function
- I/O module exchange data directly with the
processor - Desirable to allow I/O exchanges to occur
directly with memory - In some cases
42Interconnection Structures
Interconnection structures
- Collection of paths connecting various modules
called interconnection structure - All the units must be connected
- Different type of connection for different
- type of unit
- Memory
- Input/Output
- CPU
43Memory Connection
Interconnection structures
- Receives and sends data
- Receives addresses (of locations)
- Receives control signals
- Read
- Write
- Timing
44Input/Output Connection
Interconnection structures
- Similar to memory from computers viewpoint
- Output
- Receive data from computer
- Send data to peripheral
- Input
- Receive data from peripheral
- Send data to computer
45Input/Output Connection
Interconnection structures
- Receive control signals from computer
- Send control signals to peripherals
- e.g. spin disk
- Receive addresses from computer
- e.g. port number to identify peripheral
- Send interrupt signals (control)
46CPU Connection
Interconnection structures
- Reads instruction and data
- Writes out data (after processing)
- Sends control signals to other units
- Receives ( acts on) interrupts
47Interconnection Structure
Interconnection structures
- Interconnection structure support this type of
transfers - Memory to processor Processor reads instruction
or unit of data from memory - Processor to memory processor writes unit of
data to memory - I/O to processor processor reads data from I/O
device via I/O module - Processor to I/O Processor sends data to the I/O
device - I/O to or from memory
48Bus Interconnection
Bus interconnection
- Bus is communication pathway connecting two or
more devices - Characteristic of bus is a shared transmission
medium. - System bus connects major computer components
(processor, memory, I/O) - There are a number of possible interconnection
systems - Single and multiple BUS structures are most
- common
- e.g. Control/Address/Data bus (PC)
- e.g. Unibus (DEC-PDP)
49What Is A Bus?
Bus interconnection
- A communication pathway connecting two or more
devices - Usually broadcast
- Often grouped
- A number of channels in one bus
- e.g. 32 bit data bus is 32 separate single bit
- channels
- Power lines may not be shown
50Bus Structure Data Bus
Bus interconnection
- Data lines provide path for moving data between
system module - Data lines collectively called data bus
- Remember that there is no difference between
- data and instruction at this level
- Width is a key determinant of performance
- 8, 16, 32, 64 bit
51Bus Structure - Address Bus
Bus interconnection
- Address lines used to designate source or
destination of the data on the data bus - e.g. CPU needs to read an instruction
- (data) from a given location in memory
- Bus width determines maximum memory
- capacity of system
- e.g. 8080 has 16 bit address bus giving 64k
address space
52Bus Structure - Control Bus
Bus interconnection
- Control lines used to control access to and use
of data and address lines - Control and timing information
- Memory write/read
- I/O write/read
- Transfer ACK
- Bus request
- Bus grant
- Interrupt request
- Interrupt ACK
- Clock
- Reset
53Bus Interconnection Scheme
Bus interconnection
54Operation of Bus
Bus interconnection
- One module wishes to send data to another
- Obtain the use of the bus
- Transfer data via the bus
- One module wishes to request data from another
module - Obtain the use of the bus
- Transfer a request o the other module over the
appropriate control and address lines - Wait for second module to send the data
55Typical Physical Realization
Bus interconnection
56Big And Yellow?
Bus interconnection
- What do buses look like?
- Parallel lines on circuit boards
- Ribbon cables
- Strip connectors on mother boards
- e.g. PCI
- Sets of wires
57Single Bus Problems
Bus interconnection
- Lots of devices on one bus leads to
- Propagation delays
- Long data paths mean that co-ordination of bus
- use can adversely affect performance
- If aggregate data transfer approaches bus
capacity - Most systems use multiple buses to
- overcome these problems
58Multiple-Bus Hierarchies
Bus interconnection
- If a great number of devices connected to the
bus, performance will suffer - More devices attached to the bus , the greater
bus length and hence greater propagation delay - Bus become a bottleneck as the aggregate data
transfer demand approaches capacity of bus
59Multiple-Bus Hierarchies
Bus interconnection
- I/O devices attached to expansion bus
- To build high-speed bus that closely integrated
with the rest of system, requiring only a bridge
between the processors bus and high speed bus
60Traditional Bus Architecture
Bus interconnection
61High Performance Architecture
Bus interconnection
- The high speed bus brings high-demand devices
into closer integration with the processor
independent of the processor at the same time - Difference in processor and high-speed bus speeds
and signal line definition tolerated - Changes in processor architecture do not affect
the high-speed bus, and vice versa
62High Performance Architecture
Bus interconnection
63Elements of Bus Design
Bus interconnection
64Bus Types
Bus interconnection
- Dedicated bus line
- Functional dedication - Assign one function
- Physical dedication - Refers to use of multiple
bus - Connects subset of modules
- Advantage High through-put
- Disadvantage Increased size and cost of the
system - Multiplexed
- Shared lines
- Address valid or data valid control line
- Advantage - Fewer lines
- Disadvantages - More complex control Ultimate
- performance
65Method of Arbitration
Bus interconnection
- Method of arbitration needed because only one
unit successfully transmit over the bus at a time - Bus Arbitration
- More than one module controlling the bus
- e.g. CPU and DMA controller
- Only one module may control bus at one time
- Arbitration may be centralised or distributed
- Centralised Arbitration
- Single hardware device controlling bus access
- Bus Controller
- Arbiter
- May be part of CPU or separate
- Distributed Arbitration
- Each module may claim the bus
- Control logic on all modules
66Timing
Bus interconnection
- Co-ordination of events on bus
- The bus includes a clock line upon which clock
transmits a regular sequence of - alternating 1s 0s of equal duration
- A single 1-0 transmission referred to as a clock
cycle of bus cycle
67Synchronous Timing
Bus interconnection
- Events determined by clock signals
- Control Bus includes clock line
- A single 1-0 is a bus cycle
- All devices can read clock line
- Usually bus signal change on leading edge
- Usually a single cycle for an event
- Synchronous timing simpler to implement and test
- Less flexible than asynchronous timing
68Synchronous Timing
Bus interconnection
69AsynchronousTiming
Bus interconnection
- Occurrence of event depends on occurrence of
previous event - Mixture of slow and fast device
- Using older and newer technology
- Can share bus
70Asynchronous Timing
Bus interconnection
71Bus Data Transfer Types
Bus interconnection
72PCI
PCI
- Peripheral Component Interconnection
- Popular high-bandwidth,
- processor-independent bus that function as
mezzanine or peripheral bus - Delivers better system performance for
- high-speed I/O subsystems
73Example PCI Configurations
PCI
74Example PCI Configurations
PCI
75Interpretation of PCI Read Commands
PCI
76PCI Bus Lines - Required
PCI
- Systems Lines
- Including clock and reset
- Address Data
- 32 time mux lines for address/data
- Interrupt validate lines
- Interface Control
- Arbitration
- Not shared
- Direct connection to PCI bus arbiter
- Error Lines
77PCI Bus Lines - Optional
PCI
- Interrupt lines
- Not shared
- Cache support
- 64-bit Bus Extension
- Additional 32 lines
- Time multiplexed
- 2 lines to enable devices to agree to use 64-bit
- transfer
- JTAG/Boundary Scan
- For testing procedures
78PCI Commands
PCI
- The commands are
- Interrupt Acknowledge
- Special Cycle
- I/O Read
- I/O Write
- Memory Read
- Memory Read line
- Memory Read Multiple
- Memory Write
- Memory Write and Invalidate
- Configuration Read
- Configuration Write
- Dual Address Cycle
79PCI Commands
PCI
- Interrupt Acknowledge is a read command intended
for device that function as interrupt controller
on the PCI bus - The Special Cycle command used by initiator to
broadcast message to one or more targets - I/O Read and Write commands used to transfer data
between initiator and I/O controller - Memory Write command used to transfer data one or
more data cycles to memory
80PCI Commands
PCI
- Memory Write Invalidate command transfers data
in one or more cycles to memory - Two configuration commands enable master to read
and update configuration parameters in device
connected to PCI - Dual Address Cycle command used by initiator to
indicate that using 64-bit addressing
81PCI Read Operation
PCI
82Arbitration
PCI
- PCI use of centralized, synchronous arbitration
scheme - Each master has unique request(REQ), grant(GNT)
signal - Simple request-grant handshake used to grant
access to bus - Arbitration can take place at the same time that
current bus master performing data transfer - Hidden arbitration
- No bus cycles lost in performing arbitration
83PCI Bus Arbiter
PCI
84PCI Bus Arbitration Between Two Master
PCI