4' Combinational Logic Networks' 4'2 Layout Design Methods 4'2'1 Single Row Layout Design

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4. Combinational Logic Networks.4.2 Layout
Design Methods4.2.1 Single Row Layout Design

• Power rails
• Routing chnnel
• n-type, p-type row

Intra-row Routing area
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Structure of a routing channel

• Horizontal tracks and vertical tracks
• Channel Density, changed with pin
  assignment.(below)

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Layout of a full adder

• Swap the gates within each function
• Swap the XOR pair with NAND networks

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Left-edge channel routing

• Optimum under assumption that only one horizontal
  wire segment per net.

Channel that cannot be routed by the left edge
algorithm (Vertical constraint)
A dogleg wire
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4.2.2 Standard Cell Layout Design

• Cell from library
• NAND, NOR, AOI, OAI
• The same pitch (height)
• VDD and VSS lines must match up.
• External connection points are on the top and
  bottom edges.
• Cell area cannot be used for wiring.
• Feedthrough area for short cut of critical
  pathes.
• Transistor sizes are typically much larger than
  those in custom layouts.

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Wireability of placement

• Rats nest plot to identify congested area, whose
  degree of congestion will be minimized.

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4.3 Simulation

• Circuit Simulation
• Timing Simulation
• Switch Simulation
• Gate Simulation (Logic Simulation)

Propagate new value until it will be stable
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4.4 Combinational Network Delay4.4.1 Fanout

• Transistors of driving gate can be enlarged.
• Logic can be redesigned to reduce the gates
  fanout.

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4.4.2 Path Delay

• Timing Analysis identifies critical path with
  graph model, instead of exhausted search with
  logic simulator.

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Critical Path
Cutset of critical path increase transistor
size reduce wire capacitance
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False Path

• True Path determines
• timing constraint.

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Redesign for speed up
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4.4.3 Transistor Sizing
All p 1.5/0.5
1
0
1
1
0

• 0.5nsec delay/stage

All n 0.75/0.5
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Transistor Sizing (Continue)
Pull up 1.5/0.5 ? 4.5/0.5 (first stage)
3.0/0.5(other stages)
1
0
1
1
0
Pull down 0.75/0.5 ? 1.5/0.5

• 0.25nsec delay/stage
• 2 times as faster as before

0.75/0.5 ? 1.5/0.5
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Transistor Sizing (Continue)
Pull up 1.5/0.5 ? 4.5/0.5 (first stage)
3.0/0.5(other stages)
1
0
1
1
0
Pull down 0.75/0.5 ? 1.5/0.5

• 0.125nsec delay/stage
• 4 times as faster as before

0.75/0.5 ? 3/0.5
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4.5 Crosstalk

• Crosstalk depend on
• Adjacent area
• Behavior of 2 signals

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Crosstalk (continue)

• Ground wires to minimize crosstalk

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Crosstalk (continue)

• Crosstalk minimization by wire routing

Total coupling17 Total
coupling12 (a-b6, b-c6, c-d5)
(a-b5, a-d2, d-c5)
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4.6 Power Optimizationby reducing glitches
Glitch ? power

• Glitches propagate through the successive stage.
  ? the longer chain produces much glitch.

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Power Optimization (continue)

• Signal probability Ps the probability that
  signal s is 1.
• Probability of a transition Ptr,s the probablity
  that signal changes from 0 to 1 or from 1 to 0.
• Ptr,s(1-Ps)PsPs(1-Ps)2Ps(1-Ps)
• Power estimation tools based on delay independent
  assumption
• PNOT1-Pin
• POR1-(1-Pin1)(1-Pin2)
• PANDPin1 Pin2

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Logic factorization for low power
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4.7 Switch Logic Networks

• Switch Logic is not universally useful.
• Slow
• introduce hard-to-trace electrical
• problems
• lack of drive current for high
• capacitive load

• Switch network with non-constant source inputs.

Swicth implementation of a multiplexer
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Switch Logic Networks (continue)
1?0 1?0 1?0

• Output remains 1?1
• (Output should be undefined)

• Voltages are dependent on capacitance ratios,
  which cannot be controlled.
• Table shows possible voltage change of nodes.

1?0
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Switch Logic Networks (continue)Charge Sharing

• Voltages are dependent on capacitance ratios,
  which cannot be controlled.
• Table shows possible voltage change of nodes.

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4.8.1 Gate Testing

• fault model (stuck-at-0/1)

NAND
NOR
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Gate Testing (Continue)
0
1
Vector(011) for 2 NANDs stuck-at-0 test
1
1
1
1
-
Vector(11-)(-01) for 2 NANDs stuck-at-1 test
1
0
-
1
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Stuck-Open fault

• t1 stuck-open fault
• makes gate not to
• pull up to VDD.
• t2 stuck-open fault
• makes gate pull down to VSS, conditionally.
• Delay fault
• Gate delay fault
• Path delay fault

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4.8.2 Combinational Network Testing
Job1 either 1 must be set.

• Controlling the gates inputs by applying values
  to the networks primary inputs.
• Observing the gates output by inferring its
  value from the values at the networks primary
  outputs.

Stuck-at-0
Job2 Dout 0 or 1 to be observed at primary
output.
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Fault Masking

• NOR output sa0 (1) cannot be set.
• NAND output sa0 (1) cannot be observed at
  primary output.
• F(ab)b
• abb
• 0

Logic is untestable, Because of rudundant.