FPGA ??

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FPGA ??

• ? ? ?
• ????? ???????

2
????

• ??? ??? ????? ??? ALTERA?? MAXPLUS II TOOL? ????
  ?? ???? ??? ?? ??? VHDL Coding ???? ?? ????
  ?????? ?? ??? ??? ????? ?? FPGA ? ASIC ?? ??
  ????? ??? ??.

3
????

• ?? 20
• 2. ???? 30
• 3. ???? 30
• 4. ??? 20

4
?? ? ????

• ???? ??? ??? CPLD ? VHDL, ????, 2003
• Dueck, Digital Design with CPLD Applications and
  VHDL, Delmar, 2001.
• ? ???? ????
• Altera MAXPLUS II, Free download,
  www.altera.com
• M. Morris Mano and Charles R. Kime, Logic and
  Computer Design Fundamentals, Prentice Hall,
  2000.
• ???, ???, ???, ??? Altera MAXPLUS II? ??? ???
  ???? ??? ??? ??, ?????

5
????

• ??
• Altera MAXPLUS II Tool
• ?????? ??
• ????? ? ????
• ???? ??
• PLA ??
• ??? ??
• ??????
• ?? ??? ?????
• ???? ? ??? ????? ??
• ??? ???

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??

• ????
• PLDs(Programmable Logic Devices)
• ROM(Read-Only Memory)
• PLA(Programmable Logic Array)
• PAL(Programmable Array Logic)? GAL(Generic Array
  Logic)
• CPLD(Complex Programmable Logic Device)
• FPGA(Field-Programmable Gate Array)
• ASIC(Application Specific Integrated Circuit)
• Summary

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PLDs(Programmable Logic Devices)

• PLDs ROM(Read-Only Memory), PLA(Programmable
  Logic Array),
• PAL(Programmable Array Logic),
  GAL(Generic Array Logic),
• CPLD(Complex Programmable Logic
  Device), FPGA(Field-
• Programmable Gate Array)
• Programming Technology
• Permanent Type(Nonvolatile)
• Fuse(normal on) - CLOSE(intact) OPEN(blown)
• Mask programming - Mask ROM
• Antifuse(normal off) - just the opposite of a
  FUSE
• Nonpermanent Type
• SRAM bit driving n-MOS Tr. (Volatile)
• Building Look-up Table using SRAM (Volatile)
• - Logic inputs(SRAM addr.), Logic
  outputs(stored SRAM table data)
• MOS Tr. Switching Control using Floating Gate
  (Nonvolatile)
• - EPROM, EEPROM

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ROM(Read-Only Memory)

• ????
• 32 x 8 ROM ?? ???

2k x n??? ROM - k-to-2k ? Decoder - n ?? OR Gate
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ROM(Read-Only Memory)

• ????? ??
• k?? ??? ?? ??? 2k?? minterm ??
• ROM ??? OR ???

A7(I4 I3 I2 I1 I0 ) ?m(0, 2,3, ,29)
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ROM(Read-Only Memory)

• ?? ???? ?? ROM Programming

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ROM(Read-Only Memory)

• ????? ?? ??
• ??? ???? ?? ??? ??? ??? ??
• ????, ????
• ?? lt-- ??? (??? ???)
• ? 3?? 2??? ??? ??? ??

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3?? PLDs? ?? ??
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PLA(Programmable Logic Array)

• PROM? ??
• - ??? Programmable AND Array
• 3??, 4??, 2??? PLA

??? ?? X? 1 X
F1 AB AC ABC F2 (AC BC)
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PLA(Programmable Logic Array)

• PLA? ??
• - ??? ??, ? ?? ??, ??? ??
• - ? 16 ??, 48 ?? ?, 8 ??
• PLA? ??? ?? lt--???? ?
• ??? ????? ?? ????(FPLA)? ??
• ?? ? ?? ??
• - ?? ? ?? ???
• - ???? ?? ??

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PLA(Programmable Logic Array)

• ?? ??? ?? ?? ??
• F1(A, B, C) ?m(0, 1, 2, 4)
• F2(A, B, C) ?m(0, 5, 6, 7)
• ???
• F1 (AB AC BC)
• F2 AB AC ABC

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PAL(Programmable Array Logic)
??? ?? ???? ??? ??

• ??? OR ???? ??? AND ??? ? PLD
• ????? ???, ????? ??
• OTP(One Time Programmable)

PAL(Advanced Micro Devices Inc.)
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PAL(Programmable Array Logic)

• ? W(A, B, C, D) ?m(2, 12, 13)
• X(A, B, C, D) ?m(7, 8, 9, 10, 11, 12, 13,
  14, 15)
• Y(A, B, C, D) ?m(0, 2, 3, 4, 5, 6, 7, 8, 10,
  11, 15)
• Z(A, B, C, D) ?m(1, 2, 8, 12, 13)

???
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PAL(Programmable Array Logic)

• ?? ???

???
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GAL(Generic Array Logic) or Universal PAL

• ???? PAL/PLA??? OTP, ??? GAL/EPLD? ??? ???? ??
  ???? ? ? ??.(?? universal PAL).
• ???? GAL? ???? ???? ?? ??? I/O pin? ??? ? ??.(??
  PAL? ???.)
• ??? ????? ?? ? ?? Cell? ??? ????? ????? ???
  ????? ???? ??? ??? ? ??.(not Fuses).
• GAL Macrocell? ????? D-FF? 41 ?????? ????.

GAL(Lattice Semiconductor), Universal
PAL(Vantis Co.)
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GAL or Universal PAL
GAL Device Numbering

• GAL ??? 22V10??? ????. ??? 22? ?? ??? ?I/O?
  ??? ?? 10? ?? ??? ? ?? ?? ??? macrocell? ???.(V
  stands for variable or versatile
  architecture.)
• A GAL22V10? 10? ??(MC)? 12(22-10)? ?? ?? 1??
  ??? 21?(22-1)? ??? ?? ? ??.

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GAL or Universal PAL

• Macrocell for a PALCE16V8 Universal PAL

Feedback
Input
Programmable SOP array
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GAL or Universal PAL

• GAL22V10 OLMC(Output Logic Macrocell)

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CPLD(Complex Programmable Logic Device) and FPGA

• PLD? ?? ??? ????? ??? IC? ?? ??
• ?? ? ??? ??? ?? VLSI ??
• VLSI ????
• - ???? ??(Full Custom Design) ???, ??, ???
• - ?? ? ??(Standard Cell Design)
• - ??? ??(Gate Array) SOG, CMOS, BiCMOS, ECL,
  GaAs
• CPLD? FPGA
• - 1,000?? 2,000,000 ???? Gate Array? ??
• - ???? ??? ????
• - ??? ??? FF??
• - ???? ??? ?? ??(??? ?)
• - CPLD(????, ??? ???) vs FPGA(?? FFs, ??? ??)

Embeded
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CPLD and FPGA
16 Logic Array blocks - LAB 16 macrocells -
Macrocell 1FF ?? ????

• Altera MAX 7000CPLD
• EEPROM? ?? ??? ??
• EPM7128SLC84
• EPM7 MAX7000 family
• 128 macrocells ?
• S in-system programmable
• LC84 84pins PLCC

3 ?? ??
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CPLD and FPGA

• Altera MAX 7000CPLD Block Diagram

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CPLD and FPGA

• Altera MAX 7000CPLD Macrocell

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CPLD and FPGA

• Altera FLEX10K Block Diagram
• - SRAM based technology(volatile), 66MHz, up to
  200,000 gates, 0.22u 5-metal layers
• - APEX series 125MHz, up to 2,000,000 gates

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CPLD and FPGA

• Altera FLEX10K Logic Element

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CPLD and FPGA
????
I/O ??

• Actel ACT 3 FPGA
• Gate Array? ??? ??
• Antifuse ?? ?????? ???? ?????
• OTP
• ??? ?? ??? ??

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CPLD and FPGA
MUX? ?? ???? ?? - ?? 8?? ??

• Actel ? ????

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CPLD and FPGA

• Xilinx XC4000 FPGA
• - SRAM ?? ??
• - ???? ?? ??(lt-- PROM)
• - ???? ??,
• ????

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CPLD and FPGA

• SRAM ??? ??? ????? ??? ??

If (A,B,C)(0,0,0) 1st SRAM cell? ??? ?? ???l
??? SRAM cell
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CPLD and FPGA

• Xilinx? ?? ??
• - ?? ????(??, ??)
• - ??? ??(long line)
• Xilinx? switch Matrix

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CPLD and FPGA

• Xilinx ???? CLB? IOB ?? ??
• CLB(Configurable Logic Block) ???

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CPLD and FPGA

• Xilinx IOB(Input/Output Block) ??

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CPLD and FPGA

• FPGA Design Flow

Functional Simulation
Post-Layout Simulation
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ASIC(Application Specific Integrated Circuit)
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ASIC

ASIC(??) ASCP(??)
ASSP Full
Programmable Semi- ???
AV? Custom IC
custom IC IC
PLD/CPLD FPGA
Standard cell Gate array
Programmable ASIC XBlue
Xilinx IBM
ispXP
Lattice
ASCP(Application Specific Custom
Product) ASSP(Application Specific Standard
Product)
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ASIC(Application Specific Integrated Circuit)

• ASIC Design Flow

Functional Simulation
Post-Layout Simulation
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ASIC

• ASIC ??

• ?? ??? ??? ??? ??? ? ??? 6.9
• ?? ??? ??? ???? ????? 79

?? ?? ??
??(?????) ???????? 91 78
12(90)

• ??????? ASIC???? ??(????)
• - ??? 53
• - ??? TV 30

???? ADA(ASIC Design-company Association)
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EDA(Electronics Design Automation) Tool
Vendors Tools Altera MAX PLUS II /
Quartus Mentor Graphics Leonardo, IC
Graph OrCAD OrCAD Capture QuickLogic Quickworks
Summit Design Visual HDL, VHDL Synopsys FPGA
Express Viewlogic Systems ViewPLD Xilinx Foundat
ion series , Alliance Series Cadence SPW,
Verilog-XL, Composer, Gate Ensemble Avanti Hspic
e, Polaris-COM, Apollo, Compass HP HPADS(MMIC
Design) ETRI LODECAP Seodu Logic MyCAD series
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SUMMARY

• PLDs(Programmable Logic Devices)
• - ROM, PLA, PAL, GAL, CPLD, FPGA
• ASIC
• EDA Tool