The George Washington University School of Engineering and Applied Science Department of Electrical

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The George Washington UniversitySchool of
Engineering and Applied ScienceDepartment of
Electrical and Computer Engineering

• ECE122 30
• Lab 2 NAND gate design using CMOS

Jason Woytowich Ritu Bajpai September 15, 2006
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Gate Delay

• Gate Delay is the amount of time it takes a
  change of input to appear as a change on the
  output.
• Gate Delay is measured from the 50 point on the
  input signal to the 50 point on the output.

Input
Output
tp
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Gate Delay

• We also characterize the transition time of a
  signal. In this case we use the 10 and 90
  points.

90
10
tpLH
90
10
tpHL
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Gate Delay

• The load capacitance severely affects the gate
  delay.

Inv1
Inv2
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SCMOS Library

• Scalable CMOS Library
• Contains (just about) every digital logic
  component you need to build anything.
• And, Or, Xor, Nand, Nor, Xnor, Inv, Buf,
  Flip-flops, Pads, Capacitors, Resistors
• Each of these components has a specific layout
  mapped to it.
• It does not layout individual transistors.

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Objective for our simulation

• Create a NAND gate using p and n MOSFET and
  testing its performance.
• Testing the performance of a NAND gate form SCMOS
  library.
• Comparing the performance of the two NAND gates.

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Analysis/Result

• Record the rise time and fall time of both the
  NAND gates.
• Is the rise time and fall time of each gate same,
  if no then why?
• Is the rise time and fall time of both the gates
  similar to each other, if no then what could be
  the probable reasons for the difference?

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Analysis/Result

• Repeat the simulation to create a NOR gate using
  CMOS.
• In the test circuit, replace your NOR gate by the
  NOR gate in SCMOS library.
• Record the waveform in the two cases and make the
  similar observations as you made for NAND gate.