The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering

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The George Washington UniversitySchool of
Engineering and Applied ScienceDepartment of
Electrical and Computer Engineering

• ECE122
• Lab 4 VTC Power Consumption

Jason Woytowich Ritu Bajpai September 28, 2006
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Voltage Transfer Characteristic

• Vin on the X-Axis and Vout on the Y-Axis

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Voltage Transfer Characteristic

• A symmetric VTC is one where the Vin vs Vout
  curve crosses through the dead center of the
  graph.
• Using 5V inputs and outputs this point is 2.5V in
  and 2.5V out

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Lab activity

• Find Wp/Wn such that the VTC for an inverter is
  symmetric.

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Replace the pulse input by a DC source in the
inverter test circuit.
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Select DC transfer sweep analysis and select
sweep 1
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DC sweep analysis
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Choose DC results
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VTC obtained is not symmetric
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Insert commandgtanalysisgtparametric sweepgtsweep1
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Defining pMOS width as a parameter

• In the T-Spice code write the following command
• .param width35u
• And in pMOS properties change
• W28l to Wwidth

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T-Spice code
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Parametric sweep analysis waveform
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Double click on the symmetric VTC to obtain trace
characteristics.
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Designing for symmetric VTC

• Record the width of the pMOS corresponding to
  symmetric operating point.
• In this case width .8u
• In S-Edit substitute this width for the pMOS and
  perform transient analysis.

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Rise time at symmetric operation
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Fall time at symmetric operation
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Power Consumption

• Next we will use Tanner Tools to estimate the
  power consumption of a design.
• We will also identify the sources of power
  consumption.

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Power Consumption

• You already have the following test-bench

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Power Consumption

• Simulate the circuit over 2 periods with fine
  resolution (2ns)
• Show the waveforms for
• The input and output voltages
• The power provided by the power supply
• The currents drawn from the power supply and the
  capacitor

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Power Consumption10pF Load 10ns Rise and Fall
Times
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Power Consumption

• Lower the value of the capacitor to 1pF and
  resimulate

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Power Consumption1pF Load 10ns Rise and Fall
Times
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Power Consumption

• Decrease the rise and fall times of the pulse
  source to 1ns.

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Power Consumption1pF Load 1ns Rise and Fall
Times
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Home work

• Revise the work done in all the lab turns till
  now.
• Come prepared to design a half adder and a full
  adder (using half adder) on next turn.
• You will do the schematic design and extract the
  layout for the above on next turn.