Lecture 13 Partially Reversible Logic and QuasiAdiabatic Memories - PowerPoint PPT Presentation

Title: Lecture 13 Partially Reversible Logic and QuasiAdiabatic Memories


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Lecture 13Partially Reversible Logic and
Quasi-Adiabatic Memories

• Designs with partially reversible logic
• Supply clock generation
• Low-Power Memory System Design
• Summary

• Michael L. Bushnell
• CAIP Center and WINLAB
• ECE Dept., Rutgers U., Piscataway, NJ

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Partially Reversible Logic

• Common logic gates (NAND, NOR, XOR) are
  irreversible theoretical lower bound for
  isolated irreversible operation is kT
• In CMOS, lower bound related to Vth and charges
• Partially reversible logic recovers most of its
  switching energy
• Based on self-control scheme

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Diode-Based Logic Family

• Dissipates C Vdd Vth of energy
• Uses differential signaling
• Each signal its complement must be present
• Logical 0 represented by downward pulse on c
• Logical 1 represented by downward pulse on d
• Invert signals by exchanging wires
• Need 4 clock stages

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2N-2N2D Inverter/Buffer
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Inverter/Buffer Behavior

• 1st phase idle -- Clk high and outputs (c d)
  high
• 2nd phase evaluate clock ramps down to 0 V
  (inputs a b must be valid)
• If a 0 and b 1, then d follows clock down
• 3rd phase hold outputs c d are valid, can
  be sampled, input can now be changed
• 4th phase recharge Clk ramps up to Vdd

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Adiabatic AND/NAND Gate

• IS1 and IS2 transistors isolate input from output
• Replace with transmission gate reduced channel
  resistance leads to lower power dissipation
• Drawback requires 6 clock phases
• P and P only turn on during restoration

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Adiabatic Serial Adder

• P1 F2, P2 F4 for serial adder

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Measured Energy Savings

• Assume 100 efficient power supply
• Net energy flowing into circuit from power
  supply
• Difference in net energy between 2 consecutive
  cycles is energy loss in 1 full cycle
• Design 1 serial adder
• Design 2 serial adder with isolation transistor
  replaced by transmission gate

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Net Energy Function
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Buffer Gate Energy Dissipation
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6 Buffer Chain Design with Reversible Logic

• Isi Fi 2 Isi Fi 1
• Ci Fi 2 Ci Fi 1
• 6 Clock phases required for reversible logic
  example
• Reversible logic primitives may have redundant
  outputs
• Can recover 93 of energy at 1.1 MHz (100
  efficient power supply)

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6 Buffer Chain
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Simple Charge Recovery Logic

• Modified static CMOS circuit simpler
• Adiabatic circuits so far have constant energy
  dissipation, regardless of input switching
  activity
• When input activity 0, adiabatic circuit still
  dissipates constant energy, whereas static CMOS
  only has leakage current
• Necessary to switch between static CMOS and
  adiabatic circuit
• SEL selects which mode to operate in
• 2 supply phases evaluation and hold

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Adiabatic Adder
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CMOS vs. Adiabatic CMOS 2 X 2 Multiplier Energy
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Adiabatic Dynamic Logic Inverter

• For cascading, need constant voltage Vdd between
  precharge and evaluate avoids non-adiabatic
  transitions

F
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Cascaded Adiabatic Inverters

• When 1st stage latched, 2nd starts evaluating
• When 1st stage evaluating, 2nd must be adiabatic
• Need 4 clock phases, so all loops must have a
  multiple of 4 gates in the logic

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Adiabatic Dynamic NAND Gate
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Energy Recovery SRAM Core

• Can recover 75 of energy for both reads writes
• No complexity increase and low area overhead
• Add row driver to drive memory core
• Replace sense amplifiers with voltage level
  shifters
• Vhi and Vlow ramp up and down like adiabatic
  clocks
• Generated by row driver circuit

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Adiabatic Core Diagram
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Adiabatic SRAM Cell
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Adiabatic SRAM Core Operations

• Row address decoder generates row selection
  signals W0, W1, , WM-1
• Vhi, Vlow, Vword of enabled row controlled
  independently by global supply lines Ghi, Glow,
  Gword
• Vhi, Vlow, Vword of unselected rows connected to
  static supply lines Shi, Slow, and GROUND
• Does not need bit line precharger replaced by
  bit line equalizer transistor

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Row Driver Circuit
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Read Operation

• Example supplies Shi Vdd 5 V, Slow 2 V, Vt
  1 V
• SRAM in rest state all rows disabled
• Row driver Vhi 5 V, Vlow 2 V, Vword 0 V
• bit line precharged midway to 2 V
• Read operation
• Row selection applied Vword smoothly ramped up
  to 3 V by Gword
• Vhi and Vlow ramped down to 3 and 0 V,
  respectively
• If 0 stored, node A is low, node B is high
• Both M1 and M5 on, so bit follows Vlow down to 0
  V
• bit remains at 2 V, since B is gt 3 V, and Vword
  3 V, so M6 cannot turn on
• Level shifter amplifies bit line differential
  generates output
• bit reverts to rest state (2 V) by same cells
  being read

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Write Operation

• Cell bit information overwritten by bit lines
• Apply row selection, pull up Vword, pull Vhi down
  to 3 V
• Cell voltage difference now Vhi Vlow 1 V Vt
• Cell state held for columns not being written
• Low enough to flip cell state for selected
  columns
• Simultaneously ramp Vlow and bit from 2 V to 0 V
• B pulled down by bit and cell state flips
• Return to rest state Vlow and bit revert back to
  2 V, word is disabled

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Adiabatic SRAM Waveforms
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Column-Activated Memory Core

• Only activate columns we actually will read/write
• Saves energy
• Vhi and Vlow now run vertically, generated by
  column driver, implemented like row driver
• Row driver still required
• Same cell structure

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Column-Activated Core Diagram
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Memory Core Energy Dissipation

• Energy dissipated when cell written erasing
  data
• Design 1 row-based, Design 2 column-based

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Column-Based CORE Organization

• Core of M X N bits
• n bits read/written in each operation
• Ratio of effective capacitances
• In 256 X 256 block, row-activated uses 4 times
  the energy of column-activated design

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Energy Recovery NOR Address Decoder

• Only change from conventional dynamic decoder
• Precharge pMOSFETS replaced by nMOSFETs
• Rest state Vlow Vdd, all row lines at Vdd -
  Vth
• Evaluation
• Vlow swings from Vdd to 0, all row lines follow
  it down except selected line, which stays at Vdd
  - Vth

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Address Decoder Waveforms
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NOR and NAND Decoders
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NAND Adiabatic Decoder

• Operates like NOR decoder, but only 1 row
  switches
• Uses far less energy than NOR decoder
• Can be used with pre-decoding, but requires more
  clock phases
• Same decoding scheme used for both row and column
  decoders

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Energy Recovery Level Shifter I/O Buffer
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Level Shifter Operation

• Initially Vls 0, shifter disabled
• A and A equalized
• Turn on access transistors
• bit and bit arrive, build voltage difference in
  amplifier
• Vls ramped from 0 to Vdd no short-circuit
  current
• Turn off access transistors isolate
  level-shifter
• Buffer drives I/O bus
• 90 energy recovery achieved

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Overall SRAM Supply Schemes
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Optimal Voltage Selection

• Bit line energy dissipation
• Optimal voltage swing lies between 3 Vth and 4 Vth

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Row and Column-Activated Cells

• Energy recovery of 50 for both read and write

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Energy Recovery in Adiabatic Cores
Column-Activated
Row-Activated
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Decoder Transition Times
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NAND/NOR Decoder Dissipation
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Energy Efficiency of Clock Generator
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Summary

• Energy recovery circuitry produces large power
  saving
• Cost of more area and slower clock speed
• Considerations
• Highly efficient switching power supply (high Q
  factor)
• Optimize redundant signals in reversible logic
• Quasi-static CMOS circuits are most practical
• Need to change standard CMOS process for
  adiabatic logic to add necessary diodes