Gianluca Aglieri Rinella1 - PowerPoint PPT Presentation

Title: Gianluca Aglieri Rinella1


1
Development and Implementation of the Level 0
Pixel Trigger System for the ALICE experiment

• Gianluca Aglieri Rinella1
• On behalf of the ALICE Pixel Trigger Project
• 1CERN, European Organization for Nuclear Research

2
Outline

• ALICE experimental apparatus and the Silicon
  Pixel Detector
• Fast-OR signals
• Triggering with Fast-OR signals
• Pixel Trigger System
• Description
• Features
• Measurements

3
The ALICE experiment at LHC
L3 solenoid magnet

• Heavy ions collisions
• Quark gluon plasma
• Proton-proton collisions
• pt 0.6 GeV/c

4
Silicon Pixel Detector

• 120 detector modules (half staves)
• Installed in the experimental cavern

5
Readout pixel chips and Fast-OR

• Each half stave (120)
• 2 silicon pixel sensors (160x256 pixels of 425x50
  um2)
• 10 readout pixel chips (32x2568192 channels,
  13x14 mm2 bump bonded to sensors)
• 1 optical readout Multi Chip Module

• Pixel chip prompt Fast-OR
• Active if at least one pixel hit out of 8192
• Transmitted every 100 ns
• 10 on each of 120 optical links (1200)
• Low granularity, low latency pad detector
  1200 pads of 13x14 mm2

Silicon Pixel Detector
800 Mb/s G-Link
Readout MCM
Half stave
141 mm
Sensor
1
Sensor
Pixel chips
6
Triggering with SPD

• Pre-process low latency Fast-OR signals and
  generate input to contribute to the Level 0
  trigger decision
• Proton-proton
• Minimum bias
• High multiplicity trigger
• Heavy ions
• Selection of impact parameter
• Algorithms
• Boolean functions (AND/OR) of 1200 Fast-OR bits
• Topological coincidence trigger (Global OR,
  Vertex)
• Occupancy (multiplicity)
• Implementation on FPGA

7
Requirements and constraints

• Requirements
• Extract and process 1200 Fast-OR signals from 120
  optical links operating at 800 Mb/s
• Latency 800 ns
• Allow user selection of processing algorithm
• Constraints
• No interference on data readout
• System location and space occupation

8
40 m fibers 200 ns propagation delay
9
Pixel Trigger System architecture
To DAQ in control room
1200 bits _at_ 10 MHz
CTP
Processing
Fast-OR extraction
Optical splitters
120 G-Link
Pixel Trigger electronics
350 ns
200 ns
225 ns
25 ns
800 ns

• Processing time lt 25 ns
• Bottleneck data deserialization and Fast-OR
  extraction

10
Developments

• Advanced 12-channel parallel optical fiber
  receiver modules
• Devices customized by Zarlink
• 1310 nm, single mode
• Experimental validation
• Space saving

• G-Link protocol deserializers on programmable
  hardware
• Implemented and tested with advanced FPGAs
• Not fulfilling latency requirement
• Dedicated deserializer ASIC

11
Pixel Trigger system electronics

• 9U VME size processing board (BRAIN)
• Main processing FPGA (960 user I/O pins, 1513
  BGA)
• 2x5 receiver boards (OPTIN) connected as
  mezzanine boards

400 mm

• High speed optical interfaces
• Detector Data Link
• Timing Trigger and Control

Large I/O Virtex4
Optical TxRx
360 mm

• Data flow parallelism (1000 lines)
• Double Data Rate
• Digitally Controlled Impedance
• 800 impedance matched lines

TTCRx
Virtex4
USB
DDL SIU
JTAG
12
OPTIN receiver board

• 12 channels
• Parallel optical receiver module
• 12 closely packed G-link deserializer ASICs

13
BRAIN and OPTIN boards
14
Pixel Trigger system crate

• Installation, integration and commissioning with
  SPD foreseen by the end of the year

15
Control and configuration

• Status monitoring and control on ALICE DDL
  communication layer
• User selection of different processing algorithms
• Download of configuration file into local SRAM
  memory
• Reconfiguration of the processing FPGA
• Interfaces to several ALICE subsystems

Experiment Control
Central Trigger Processor Control
Silicon Pixel Detector Control
DDL
Pixel Trigger servers (control room)
16
Latency measurement

• Serialization, deserialization, processing
  latency
• Hardware emulator of the Silicon Pixel Detector
  as data source
• Overall latency 800 ns

215 ns
17
Conclusions

• The ALICE Pixel Trigger system allows to use the
  prompt Fast-OR outputs of the Silicon Pixel
  Detector for the Level 0 trigger decision
• Minimum bias and multiplicity trigger
• ALICE the only experiment at LHC to include the
  vertex detector in the first trigger decision
  from startup
• The Pixel Trigger system
• Challenging design including innovative
  developments
• Highly compact, dense and parallel architecture
• 800 ns latency
• Hardware ready
• Firmware and software development ongoing

18
Spare slides
19
References

• References
• ALICE collaboration, ALICE physics Performance
  Report, CERN-LHCC-2003-049, J. Phys., G30 (2004)
  1517-1763
• J. Conrad et al., Minimum Bias Triggers in
  Proton-Proton collisions with the VZERO and
  Silicon Pixel Detectors, ALICE Internal note,
  ALICE-INT-2005-025, 19/10/2005
• G. Aglieri Rinella et al., The Level 0 Pixel
  Trigger system for the ALICE experiment, Journal
  of Instrumentation JINST 2P01007
• A. Kluge, The ALICE Silicon Pixel Detector
  front-end and readout electronics, NIM A 560
  (2006) 67-70

20
Angular resolution
21
Trigger algorithms

• Combinational (boolean AND/OR) functions of 1200
  Fast-OR bits
• Occupancy (multiplicity)
• Coincidence trigger (topology)
• Not possible iterative algorithms on data set
• Example vertex trigger
• Pseudo-Tracklet one chip hit on inner and one on
  outer layer, in line with region /-10 cm around
  vertex
• Chip map for pixel trigger electronics calculated
  from simulation (L11,L21), (L12, L22), , (L1n,
  L2n)
• FPGA looks for at least 1 out of 11000
  pseudo-tracklets
• Processing time 12.4 ns (Xilinx ISE)
• 4 of FPGA resources (Xilinx ISE)
• FPGA counts how many out of 11000 tracklets are
  present
• 27 ns processing time (Xilinx ISE)
• 5 of FPGA resources (Xilinx ISE)

22
Multiplicity trigger
Jan Fiete Grosse Oetringhaus
23
Radiation effects

• Radiation Results of the SER Test of Actel,
  Xilinx and Altera FPGA instances, iROC report,
  2004
• Failure In Time (FIT) errors in 109 hours with
  neutron flux of 14 cm-2hr-1
• SEFI Single Event Functional Interrupt
• SEU Single Event Upset (configuration)

FIT SEFI SEU
Altera EP1C20 453
Xilinx XC3S1000 320 1240
Xilinx XC2V3000 1150 8680

• Neutron max fluence 2.0 108 cm-2 (10 y)
• Morsch, Pastircak, Radiation in ALICE Detectors
  and Electronic Racks, ALICE-INT-2002-28
• Central Trigger Processor using SRAM based ALTERA
  Cyclone EP1C20

Errors in 10 years SEFI SEU
Altera EP1C20 7
Xilinx XC3S1000 5 18
Xilinx XC2V3000 17 124
24
ALICE trigger parameters
Level 0 Level 1 Level 2
Last trigger input at CTP (ms) 0.8 6.1 87.6
Trigger output at CTP (ms) 0.9 6.2 87.7
Trigger input at detectors (ms) 1.2 6.5
Rate (Hz) 1000 40-800
25
The ALICE experiment at LHC
L3 solenoid magnet
Dipole magnet

• Heavy ions collisions
• Quark gluon plasma
• Proton-proton collisions
• pt 0.6 GeV/c