Unit 4 Overview of Wafer Fabrication

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Unit 4 Overview of Wafer Fabrication
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Overview of Wafer Fabrication

• Four stages of Semiconductor Manufacturing
• material prep
• crystal growth and wafer prep
• wafer fabrication
• packaging
• Wafer Fabrication
• the series of processes used to create the
  semiconductor devices in/on the surface of the
  wafer

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Wafer Terminology

• Chip, die, microcircuit, die,bar
• the identical circuits covering the wafer
• Scribe lines, saw lines, streets, avenues
• small areas between the chips used to separate
  them
• Engineering die, test die
• special devices or circuits containing special
  chemicals to be tested during processing
• Edge die
• partial die patterns that will not function

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Wafer Terminology (cont.)

• Wafer crystal plane
• the crystal structure toward which the chip edges
  are oriented
• Wafer Flats
• the flatted edge which indicates the crystal
  structure and material type

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Basic Wafer Fab Operations

• Layering
• Patterning
• Doping
• Heat Treatments

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Layering

• Adding thin layers to the wafer surface
• either insulators, conductors or semiconductors
• deposited by two major techniques - growing or
  deposition
• Oxidation - growing a silicon dioxide layer on
  the wafer surface
• Deposition - common techniques are CVD (chemical
  vapor deposition) Evaporation and Sputtering.

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Patterning

• Series of steps resulting in removal of certain
  portions of the added surface layers
• After removal a pattern of the layer is left on
  the wafer surface.
• Material removed may be in the form of a whole or
  just an island of material.
• Patterning process known by names Litho, Masking,
  Photolithography, Photomasking, Microlithography
• Patterning is the most critical basic operation.

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Patterning (cont)

• Goal is to
• create circuit parts in the exact dimensions
  (feature size) required by the circuit design
• locate them in their precise location on the
  wafer surface.
• Errors in process or placement can change the
  electrical functions of the device.
• Contamination can introduce serious defects that
  result in loss of good die.

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Doping

• Places specific amounts of dopant in the wafer
  surface through openings in the surface layer.
• Two techniques used are Ion Implantation and
  Thermal Diffusion.
• Thermal diffusion - chemical process that takes
  place when wafer is heated to about 1000 C and
  exposed to vapors of the proper dopant.
• Ion Implantation - physical process in which
  dopant atoms are ionized, accelerated to high
  speed and shot into the wafer surface

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Doping (cont)

• Purpose
• create either N type or P type pockets in the
  wafer surface
• these pockets form the PN junctions required for
  operation of the transistors, capacitors, diodes
  and resistors in the circuit

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Heat Treatment

• Heat treatment to achieve specific results.
• Annealing -
• heat treatment (about 1000 C) occurring after
  ion implantation to repair disruptions in the
  wafer crystal structure.
• Alloying -
• occurs after metal conductor strips placed on
  wafer. Metal alloyed (about 450 C) to wafer
  surface to ensure good electrical conduction.

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Semiconductor ManufacturingProcess Steps

• Hundreds of steps are often required in the wafer
  processing of an I.C.
• The four basic operations are used repeatedly to
  build the parts of the device in and on the wafer.

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Building an MOS Transistor

• Circuit Design
• Block diagram of the circuit
• Schematic
• Circuit layout - using CAD of the composite
  (composite - the entire circuit including every
  layer)
• The drawings are separated into layers and
  digitized (translating to a digital database)
• Final drawing completed on a computerized X-Y
  plotter table

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Reticles and Mask

• Reticle -a hard copy of the individual drawing
  recreated in a thin layer of chrome deposited on
  a glass or quartz plate.
• May be used directly in the photo process or used
  to make a photo-mask or mask.
• Masks are used to pattern a whole surface in one
  pattern transfer. Masks and reticles are similar
  in makeup.
• Reticles and Masks are produced in a separate
  department or purchased from an out side vendor.
• A Mask setis supplied for each type of circuit.

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Semiconductor Manufacturing

• Wafer Fabrication Overview

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Wafer Fabrication Overview

• Layering
• Patterning
• Doping
• Heat Treatment

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Layering Operation

• Thin layers of either conductor or insulator
  material are added to a wafer of silicon using
  one of two techniques.
• Grown
• Oxidation
• Nitradation
• Deposited
• Chemical Vapor Deposition
• Evaporation
• Sputtering

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Patterning

• Series of steps to remove oxide from a new layer
  to begin to form the circuit path.
• These processes are known as Lithography, Masking
  or variations of those names.
• The repeating of this process creates the surface
  parts of the device that make up the circuit.
• A most critical operation - sets dimensions for
  device

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Doping

• Process whereby specific amounts of dopant are
  embedded in the wafer through openings in the
  surface layers.
• Thermal Diffussion and Ion Implant are two
  techniques commonly used to accomplish this.

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Heat treatment

• Operations in which the wafer is heated and
  cooled to obtain two specific outcomes,
  annealing and alloying.
• Annealing is the repair of a wafers crystal
  structure after ion implant has disrupted it.
• Alloying is heat treating the wafer after metal
  deposition to ensure good electrical conduction.

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Layering Step 1

• The Step - This first layer, called Field or
  Start Oxide, is a layer of silicon dixoide grown
  on a wafer through a process known as oxidation.
• The Purpose - for protection and the creation of
  a doping barrier.
• The Method - Thermally grown in a diffusion
  furnace.
• The Illustration - Shows the new layer above the
  silicon substrate of a new wafer.

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1) Layering - field oxide
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Patterning Step 2

• The Step - This pattern process leaves two holes
  in the field oxide known as source-drain holes
• The Purpose - These holes define the source and
  drain areas of the transistor.
• The Method - Photolithography, including masking
  process of spin, expose, develop of the pattern
  and etch to remove unwanted oxide.
• The Illustration - shows the oxide removed to
  form the pattern.

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2) Patterning - source drain holes
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Doping Step 3

• The Purpose -these pockets will form the P-N
  junctions required for the construction of diodes
  and transistors
• The Step - creates two N type pockets in the
  wafer surface.
• The Method - pockets formed through diffusion
  process and driven deeper through reoxidation
• The Illustration - shows resultant Npockets
  (green) and new oxidation layer.

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3) Doping LayerN-type doping and reoxidation of
source - drain
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Patterning Step 4

• The Step - patterning is used to remove the field
  oxide in the gate region.
• The Purpose - preparing the device for the
  construction of the gate region.
• The Method - spin, expose, develop and etch to
  form the new region.
• The Illustration - shows the material removed
  forming the gate region.

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4) PatterningGate region is formed
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Layering Step 5

• The Step - exposed silicon in gate region and
  source and drain holes are reoxidized.
• The Purpose - preparation for contact holes into
  source and drain regions.
• The Method - thermal oxidation in a heating
  furnace.
• The Illustration - the area above the source and
  drain regions shows oxide layer.

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5) LayeringGate oxide is grown
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Patterning Step 6

• The Step - two holes are patterned in the
  reoxidized source and drain regions.
• The Purpose - contact holes to connect the
  metalization layer to the source and drain
  regions.
• The Method - spin, expose, develop and etch
• The Illustration - shows the path opened to the
  source and drain regions.

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6) Patterning Contact holes are patterned into
source/drain regions
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Layering Step 7

• The Step - deposition of a layer of metal across
  the entire surface of the wafer.
• The Purpose - to provide a conduction path to the
  source, drain and gate regions.
• The Method - low pressure chemical vapor
  deposition (LPCVD).
• The Illustration - shows the metal layer
  overlaying the entire device.

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7) Layering Conducting metal layer is deposited
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Patterning Step 8

• The Step - patterning the wafer to define the
  circuit path.
• the Purpose - removal of unwanted metal to reveal
  electrical path for circuit operation.
• The Method - metal etch using high energy plasma
  generated in RF field.
• The Illustration - the metal conduction layer
  shown in blue above the source, drain and gate
  regions.

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8) Patterning Metal layer is patterned
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Heat Treatment (Alloy) Step 9

• The Step - wafer is heated to alloy the metal to
  the exposed source and drain regions.
• This Purpose - ensures good electrical contact.
• The Method - annealing in a nitrogen gas
  atmosphere.
• The Illustration - the device appears the same.

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9) Heat Treatment Metal is alloyed to layer
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Layering Step 10

• The Step - application of a passivating layer
• The Purpose - to protect the wafer surface during
  testing and packaging.
• The Method - a polyimide spin which includes a
  curing process in diffusion.
• The Illustration - Shows the final protective
  layer.

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10) Layering Protective passivation layer is
deposited
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Pad Mask Step11

• The Step - patterning process removing the
  passivating layer from over the terminal pads on
  the periphery of the chip.
• The Purpose - to provide electrical to the chip
  through the passivatiom layer.
• The Method - a more involved masking process to
  remove the unwanted polyimide.
• The Illustration - the opening above the bond pad
  is shown.

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11) Patterning Passivation layer is removed over
metal pads
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Electrical Test and Sort

• The Steps - wafer is electrically tested for each
  component of the process and sorted for speed and
  functionality
• The Purpose - to determine if process is correct
  and functionality and speciifcations of each
  device.
• The Method - electrical test and sort test each
  device on the wafer in a systematic method.

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Wafer Sort

• Each chip is electrically tested for continuity
  and functionality
• Wafer is mounted on a vacuum chuck and aligned to
  thin electrical probes that contact each bonding
  pad on the chip.
• Wafer probers are automated so that after
  aligning with an automatic vision system to the
  first chip the entire sequence is completed
  without operator assistance.

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Wafer Sort (cont)

• Goals of wafer sort
• Identification of working chips before they go
  into packaging
• Characterization of the electrical parameters of
  the device (engineering tracking of device
  performance)
• Yield determination (good vs bad or
  non-functioning die) used for feedback to process
  engineering.
• Bad die are usually marked with an ink dot or
  located on a computer map of the wafer.

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Packaging

• Sorted wafers are then moved to packaging.
• This may be off shore or in another part of the
  facility,
• The wafers are sawn imto chips with a diamond saw
  and the good die separated from the bad
• The chips are them mounted into lead frames and
  die attached.
• The bond pads are wired bonded and the package is
  finally sealed.