RCU Status

1
RCU Status

• HiB, UiB, UiO

• RCU design
• RCU prototypes
• Firmware/software
• FEE-board test
• TPC sector test
• Towards final version

2
1. RCU design control flow
TTCrx
SIU controller
FEE bus controller
DDL command decoder

• State machines

FEE SC
RCU resource priority manager
Huffman encoder
DCS low level
Watchdog 2
Watchdog 1 health agent
Debugger
DCS high level
PCI core
3
RCU design - data flow

• Shared memory modules

TTC controller
TTCrx registers
FEE bus controller
Event memory 1
Event memory 2
SIU controller fifo
FEE bus controller
Event fragment pointer list
SIU
Huffman encoder
FEE bus controller
Configuration memory
DCS
4
2. RCU prototypes

• Prototype I
• Commercial OEM-PCI board
• FEE-board test (ALTRO FEE bus)
• SIU integration
• Qtr 3, 2001 Qtr 2(3), 2002
• Prototype II
• Custom design
• All functional blocks
• PCB Qtr 2, 2002
• Implementation of basic functionality
  (FEE-board-gt SIU) Qtr 3, 2002
• Implementation of essential functionality
  Qtr 2, 2003
• (Prototype III)
• SRAM FPGA -gt masked version or Antifuse FPGA (if
  needed)
• RCU production
• Qtr 2, 2003

5
RCU prototype II

• Implementation of essential functionality
• Custom design
• All functional blocks

FEE-bus
DCS
DCS
TTC rx
FEE-bus
FEE SC
PCI bus
PCI core
FPGA
SIU
internal SRAM
SIU-CMC interface
gt 8 MB
FLASH EEPROM
Memory D32
6
RCU prototype II - layout

• Motherboard
• FPGA
• memory data buffer
• memory work space
• ethernet
• PCI interface
• CMC connectors
• Mezzanine card I
• SIU
• Mezzanine card II
• FEE bus A and B
• TTCrx
• Profibus interface

7
RCU prototype II - motherboard
8
RCU prototype II mezzanine cards
SIU mezzanine card (1/2 CMC)
9
RCU prototype II - status

• Floor plan of PCI board

• Status motherboard (in collab. with HD)
• design and layout done
• PCB production in May
• mounting of components in May/June
• testing debugging

107 mm
314 mm
10
(No Transcript)
11
(No Transcript)
12
RCU prototype II - status

• Status mezzanine boards
• SIU (needs adapter)
• FEE-bus, TTCrx, Profibus
• design done
• layout and PCB production in May

13
RCU prototype II - status

• TTCrx

14
RCU prototype II - status

• Profibus

15
RCU prototype II - status

• FEE-bus
• two branches
• external multiplexing
• internal (inside FPGA) multiplexing (modified
  mezzanine board)

16
3. Firmware/software status and plans

• Test environment for FEE-boards
• TPC sector test
• Towards the final version

17
FEE test environment

• Special RCU not TTCrx, no DCS, no SIU

GUI?

• Application program
• C/C
• GUI?

PC LINUX RH7.2
RCU/ALTRO test tool
RCU-API
device driver
PCI core mailbox memory
PCI FPGA board
FEE bus controller
tester
FEE bus
Signal generator
FEE-board (ALTRO)
18
RCU system for TPC test 2002/2003

• Readout of 4 FEE-bus branches
• 2 RCU prototypes II
• fallback solution 4 (2) RCU prototypes I (3
  boards are available)
• Basic RCU functionality
• configure FEE (done)
• readout event (being debugged)
• develop logics for readout of all FEE cards on
  FEE-bus
  (design in progress)
• include external SRAM
  (designed, simulated, being tested)
• develop RPM for controlling data transfer from
  FEE-bus to SIU
  (design started)
• Include simple trigger and event-ID
• Interface to DATE
• DAQ via DDL
• 2 pRORC (including SIU DIU)
• Integration of pRORC DATE 4 (June 2002)
• fallback solution DAQ via RCU-PCI

19
RCU system for TPC test 2002/2003
FEE-boards
RCU prototype II/I
Trigger
FEE-bus
LINUX RH7.2 FEE configurator PLDA/PCI-tools RCU-AP
I device driver
SIU
FPGA
interface
FEE-bus controller SIU controller
Manager
PCI core
SIU
SRAM
FLASH
ext. SRAM
PCI bus
DDL
pRORC
DIU
LINUX RH7.2 DATE 4 DDL/PCI-tools pRORC-API device
driver
PCI bridge
Glue logic
interface
DIU
PCI bus
20
Towards the final version

• Radiation induced corruption of SRAM
• SEE in configuration SRAM of FPGA will happen
• monitor system state and detect such effects
  -gt reset FPGA
• two watchdogs
• FPGA self-detection
• detection by Profibus slave ASIC
• DCS
• two level interface
• Profibus slave controller (ASIC)
• ethernet chip
• Trigger
• one TTCrx per RCU