TPC FEE Status and Planning

1
TPC FEE Status and Planning CERN, 7th March 2005

• Content
• Introduction
• Status and Milestones
• PASA, ALTRO
• FEC
• Readout Control Backplane
• Readout Control Unit
• Installation

2
System Overview
power consumption lt 40 mW / channel
DETECTOR
Front End Card (128 CHANNELS)
drift region 88ms
Custom Backplane
Kapton cable
8 CHIPS (16 CH / CHIP)
8 CHIPS (16 CH / CHIP)
ALTRO
gating grid
Digital Circuit
PASA
RCU
ADC
RAM
anode wire
CUSTOM IC (CMOS 0.35mm)
pad plane
570132 PADS
CUSTOM IC (CMOS 0.25mm )
(3200 CH / RCU)
CSA SEMI-GAUSS. SHAPER

• BASELINE CORR.
• TAIL CANCELL.
• ZERO SUPPR.

1 MIP 4.8 fC S/N 30 1 DYNAMIC 30 MIP
10 BIT lt 12 MHz
MULTI-EVENT MEMORY
GAIN 12 mV / fC FWHM 190 ns
3
PASA Production and Test Summary
Production Engineering Data
INPUTS

• process AMS CMOS 0.35 mm
• area 18 mm2
• MPR samples Jan 02
• ER samples (500 chips) Sep 03
• full delivery (49359 chips) Jan 04
• Completion of mass test May 04
• yield (working chips) 94
• yield 83 CG lt 5, PTlt5, BSL lt 5

single channel
OUTPUTS
4
ALTRO Production and Test Summary
5
Front End Card 1/4
Top Side
6
Front End Card 2/4

• Production of 4800 FEC
• Contract signed in Dec 03 (Note-Xperi _at_ Lund)
• Pre-series of 50 boards with good quality (Feb
  04)
• Pre-series of 200 boards (May 04)
• Full production (according to flexible schedule)
  started in Aug 04
• Production rate 400 boards/ week
• Nr. of boards produced 3000
• Production quality is sampled at CERN by testing
  5x lots of 50 boards (5 of the full production)
• Yield gt 90

Production
Bottom Side
Milestone 398, FEECards End Production Apr 05
7
Front End Card 3/4
COOLING PLATES (COPPER)
Kapton Cables
COOLING PIPE
Milestone 230, FEE cables

• Production of 4500 copper plates in
• progress. Half have been produced
• Delivery 1st lot Dec 04, 2nd lot Mar 05

• Production of 30K kapton cables completed
• Full delivery end Nov 04

8
Front End Card 4/4

• Test Procedure
• Verification of the supply voltages and currents
• Combination of the PASA and ALTRO tests
• Test of FPGA, Readout and Control Network
  interfaces
• Burn-in tests T 0 - 100C cycles
• All information will be stored in the ALICE
  Construction Database

Mass Test
Bottom Side

• Status
• Hardware test bench and test procedures
  (semi-automatic) fully operational
• Software
• Control and Acquisition ready
• Analysis ready
• Test results Logging ready
• Projected test rate 80 boards / dd ? 1600
  boards / mm

Milestone 239, FEECards Test, Mar - Jun 05
9
Readout Control Backplane 1/3
FEC SIDE (close-up view)
10
Readout Control Backplane 2/3
Readout and Control Backplane
25 Front End Cards
Power Connector
PASA
Readout Partition (3200 channels)
ALTRO
11
Readout Control Backplane 3/3
Production

• All backplanes (24 PCBs) are ready for production
  (864 pcs)
• Mechanical test OK
• Electrical Test OK
• Integration Test in SSW OK, with new RCU OK
• Production database submitted to several
  Manufacturers
• Test Bench for mass test ready
• Test Software in progress
• Production will start after integration test with
  final RCU (Apr 05)

Milestone 394, FEE bus End Production Jul 05
12
Readout Control Unit 1/7
Excalibur ARM-Processor
DCS BOARD (HEIDELBERG)
READOUT CONTROL UNIT (BERGEN CERN)
DDL SIU (DAQ)
13
Readout Control Unit 2/7
Radiation Tolerance Strategy

• Decide to migrate RCU-FPGA to XILINX
• SEU per Run (4 hours) 3.7 gt Not acceptable
  without reconfiguration
• ALTERA FPGAs do not provide real-time readback of
  configuration data
• Partial configuration while running upon error
  detection
• Decide to keep DCS board unchanged
• Port RCU design to new development environment
• Redundancy / triple voting schemes for vital
  circuits
• Verify expected performance under irradiation
• XILINX test _at_ OCL in August 04
• System test _at_ TSL Q1 205 with large beam spot in
  May 05

14
Readout Control Unit 3/7
TOP SIDE
DDL-SIU PMC Connectors
Power Regulators
DCS Interface
15
Readout Control Unit 4/7
BUS TRANSCEIVERS
BOTTOM SIDE

• FPGA MAIN FUNCTION
• Power-On Procedure
• FEE Initialization
• Dataflow Control
• FEE Safety Control

RCU to FECs CONNECTORS
FPGA XILINX Virtex-II Pro

• Reconfiguration Support Elements
• FLASH MEM
• ProASIC plus

16
Readout Control Unit 5/7
FINAL PROTOTYPE
17
Readout Control Unit 6/7
Firmware
RCU FPGA
TRIGGER INTERFACE
CONTROL NETWORK
F E E
TO DCS BOARD
READOUT NETWORK
DATA ASSEMBLER
SIU INTERFACE
TO SIU BOARD

• Firmware meets all basic requirements
• Dataflow and Slow Control functions
• Maximization of available bandwidth
• Specific Macros speed up FEE initialization
• Eventual updates are expected

18
Readout Control Unit 7/7
New RCU Status

• Schematic capture Nov 04 OK
• PCB Layout Nov 04 OK
• FPGA Test board Nov 04 OK
• Board ready for test Feb 04 OK
• Qualification of final RCU Feb Mar 05

Milestone 231, RCU Start Production Apr 05
Milestone 395, RCU End Production Jun 05
Milestone 236, RCU Test Jul-Oct 05
INSTALLATION ELECTRONICS (247) Nov 05 Feb
06
19
Beam test _at_ CERN May 2004 (T10)

• IROC in Field Cage prototype readout with
• 43x FECs ( 5500 channels 1 of Alice TPC )
• 2x RCU ( DCS SIU) cards
• TTC clock / trigger distribution
• Full DAQ system with link to HLT
• Final Power supply distribution Wiener500 with
  40m cables

20
Noise Level Full IROC
Noise average level 0.65 ADC counts
(r.m.s.) 700 e- TDR lt1000e-
21
Installation Procedure 1/2
Engineering drawings (GSI)
OROC
3-sector model
Service Support Wheel
IROC
22
Installation Procedure 2/2

• FECs are tested separately by means of a
  dedicated mounting test tool (FEC to USB
  interface)
• Measurement of VCCA, VCCD, IA, ID
• Test of all CSRs, Control Readout path
• Initialization of the FEC
• Generation of the trigger and clock signals
• Readout of cathode wires pulsed signals

23
Conclusions

• FEC
• gt70 cards produced
• Projected yield above 90
• Start of testing
• RCU
• New RCU currently under test
• Mechanic constraints have been successfully
  verified
• Ongoing testing show interfaces to DDL and FEC
  are functioning
• DCS interface and reconfiguration scheme are
  being tested
• No bottleneck or point of concern
• The Front-end Electronics is on track for
  installation

24
Backup
Each of the 36 TPC Sectors is served by 6 Readout
Partitions
PASA ALTRO
COUNTING ROOM
ON DETECTOR
FEC 128 ch
13
Readout bus ( 200 MB / s )
2
FEC 128 ch
RCU
FEC 128 ch
1
Data Proc. and Memory
DDL ( 200 MB/s )
Bus controller ( conf. R/O )
DETECTOR
DAQ int. (DDL-SIU)
DCS ( 1 MB/s )
FEC 128 ch
12
BOARD Controller
DCS int. (Ethernet)
Local Monitor and Control
TTC optical Link (Clock, L1 and L2 )
Trigger int. (TTC-RX)
2
FEC 128 ch
Control Network (I2C-serial link)
FEC 128 ch
1
Overall TPC 4356 Front End Card 216
Readout Partitions
25
Backup
Tool for the insertion of the kapton cables
Mass Test
26
Backup
Mass Test
FEC TESTER (Frankfurt)
27
Backup
28
Backup
SEU in RCU FPGA

• SEU in RCU FPGA

• Errors per run (4 hours) per TPC system

29
Backup
New Measurements

• SEFI test with Xilinx Virtex-II Pro FPGA
• reconfiguration started after 200 seconds
• errors are corrected continuously

• Test conditions
• Flux 1.5 x 107 protons/(cm2.s)
• Reconfiguration time 5 s
• Real life
• Flux 7.9 x 102 hadrons/(cm2.s)
• Reconfiguration time 10 ms
• Duty cycle gt106 times better in real life

30
Backup
TOP SIDE
Test Connectors
DCS Interface DIMM connector
DDL-SIU PMC Connectors
Power Regulators
31
Backup
BOTTOM SIDE
RCU to FECs CONNECTORS
BUS Transceivers
FPGA Altera APEX20K400E