SCI: Serial Communications Interface

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SCI Serial Communications Interface

• Mauricio Ballesteros
• Rob Bush
• John Smartt

November 7, 2000
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Serial Communication Interface

• Overview (John)
• Description
• ACIA
• Data format and Example
• HC11 Specifics (Mauricio)
• Registers
• Noise
• Wake modes
• Transmitter and Receiver (Rob)
• Send / Receive process
• Interrupts
• Noise Cases

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Data Transmission

• Importance
• Most electronic devices must communicate with
  other devices to either control them or send data
  to them
• Standardization
• The two communicating devices must speak the
  same language
• Key Features
• Compatibility
• Data Integrity
• Speed

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Two Modes of Transmission

• Parallel
• Simultaneous 8-bit transmission
• Requires 8 data lines
• Faster than Serial transmission
• Serial
• Transfers 1 bit at a time
• Requires only one data line
• Can be used to connect to a terminal or PC

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Asynchronous Communications Interface Adapter
(ACIA)

• Permits serial transmission with one data line
• Acts as both a serial-to-parallel converter and
  as a parallel-to-serial converter
• Chip-to-ext is parallel-to-serial
• Ext-to-chip is serial-to-parallel
• Uses PD0-PD7

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Serial Transmission

• Synchronous Peripheral Interface (SPI)
• Transmitter and receiver must be synchronized
• Data rates are dependent on clock rates
• Flexible enough to interface with many devices
• Asynchronous Serial Communication (SCI)
• Start and stop bits are used to define words
• Often used for telephone communication (through a
  modem)

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Start and Stop bits

• Start bit
• First bit to be transmitted for each word of data
• Indicates the beginning of a word
• Usually detected as a transition from 1 to 0
• Stop bit(s)
• Last bit(s) of a word
• Indicates the end of a word
• Usually 1

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Parity Bit

• Used to ensure that no bits have been lost
• Odd parity indicates an odd number of 1s
  including the parity bit
• The sum of the 1s (including the parity bit)
  will be odd
• Even parity indicates an even number of 1s
  including the parity bit
• If two bits are altered by noise, the error will
  not be detected by the parity check

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Pulse Train Example
4410 (001011002)is to be sent with one start
bit, even parity, 8-bit word length, and two
stop bits LSB is always sent first
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Baud Rate

• Baud rate is set in the BAUD register and defines
  the time period for bit detection
• Baud is the reciprocal of the shortest pulse
  duration in a data word, including start, stop,
  and parity bits
• Bit rate is often confused with baud rate, but it
  refers only to the number of data bits
  transferred per second

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Baud Rate Example

• Given
• Baud rate 4800 (baud/sec)
• 12 bits/word 1 start, 2 stop, 1 parity, 8 data
• Results
• Bit time 1/(baud rate) .208 msec
• Word time (12 bits)(bit time) 2.5 msec
• Word rate 1/(word time) 400 word/sec
• Bit rate (word rate)(8 data bits) 3200
  bits/sec

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Baud Rate Control Register

• Sets the baud rate of both the transmitter and
  receiver
• SCPx and SCRx bits are used to scale the E-clock
  to the required baud rate
• TCLR and RCKB are for factory use only

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Noise Effects

• Noise Detection
• If three samples taken in near the middle of the
  bit time do not agree.
• During the reception of the start bit, 4
  additional samples (start bit qualifiers) are
  taken. If all seven samples are not 0 noise is
  detected.
• Single noise signal affecting a data bit would be
  detected by paring.
• Double noise will not be detected by paring.
• Noise signals before the starting bit also
  creates a problem if parity is used.

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SCI General Description

• Universal Asynchronous Receiver Transmitter
• Utilizes a Standard nonreturn-to-zero (NRZ)
  format
• One start bit
• 8 or 9 data bits
• One stop bit
• Transmitter and receiver are functionally
  independent
• same baud
• same data format
• Detects noise errors
• Baud Rates
• Standby mode
• Full Duplex

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SCI Registers and Control Bits

• SCI system is configured by 7 registers
• Mainly BAUD, SCCR1 and 2, SCSR, SCDR.
• Port D data direction (DDRD) and SPCR

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SCI Data Register (SCDR)
It contains the data to and from the MCU
SCDR
102F

• It is two separate registers
• When the software reads to SCDR?RDR read-only
  receive
• When the software writes to SCDR?TDRwrite-only
  transmit

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SCI Status Register (SCSR)
The SCSR generates hardware interrupts and
indicate errors in the reception of characters.
SCSR
102E

• Contains two transmitter status flags

• Five receiver-related status flags.

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SCSR cont.

• Definitions
• TDRETransmit Data Register Empty
• 0not empty. A character in the Transmitter data
  Register has not been transferred to the transmit
  shift register.
• 1the SCDR can accept new data. It is checked
  before each new character is sent.
• TC Transmit Complete
• 0transmitter is busy sending a character,
  preamble or break.
• 1transmitter is in idle state. It has completed
  the sending process.
• RDRF Receive Data Register Full
• 0Not full nothing has been received since last
  reading of SCDR.
• 1the character has been received and is ready to
  be read by software.

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Definitions cont.

• IDLE Idle-Line Detect
• 1it has become idle?full character line of 1s.
• OR Overrun Error
• 0no overrun error.
• 1overrun error has occurred. This error is
  caused when a character is received but the
  previously received character was not yet read.
  The new character is lost, and the other is
  read.
• NF Noise Flag
• 0no noise detected.
• 1data logic recovery detected noise during
  reception of the character in the SCDR.
• FE Framing Error
• 0no error detected
• 1framing error detected in the SCDR?if a 0 is
  detected where a 1 was expected during the stop
  bit is caused by the improper alignment of the
  character reception frame with incoming serial
  data.

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SCCR1 Control Register 1

• Includes 3 bits associated with the optional 9
  bit data format and the WAKE bit.
• Receiver or Transmitter extra bit
• Wake
• Character length
• M SCI character length
• 0one start bit, 8 data bits, one stop bit
• 1one start bit, 9 data bits, one stop bit
• note the M1 is used for an extra stop bit.
• R8When configured for 9 bits data character, R8
  acts as an extra 9 bit.

102C
SCCR1
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Cont.

• T8acts as an extra 9 bit of the Transmitter data
  Register when it is configured to 9 bits data
  character.
• WAKEWake-up Method Select
• 0idle line detection
• 1Address mask

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SCCR2 Control Register 2

• The main control register for SCI subsystems.

102D
SCCR2
Wake-up control
Transmitter and receiver enable control.
Generate Breaks
Local interrupts enable control whether the SCI
status flags will be polled or generate hardware
interrupts.
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Definitions

• TIE Transmit Interrupt Enable
• 1An SCI interrupt requested if TDRE1
• TCIETransmit Complete Interrupt Enable
• 1 TCIE interrupts enable if TC1
• RIE Receive Interrupt Enable
• 1 SCI receive enable when either RDRF or OR 1
• ILIE Idle-Interrupt Enable
• 1IDLE interrupt is requested when IDLE1
• TE Transmit Enable
• 1SCI transmit enable
• RE Receive Enable
• 1SCI receive enable
• RWU Receiver Wake Up
• 1wake up enable
• SBK Send Break
• 1enable to send synchronous breaks

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Port D and Data Direction

• The SCI register uses the two LSBs of port D.
• The internal subsystems overrides other pin
  controls to take control of the pin.
• Receiver Enabled
• Bit 0 of the DDRD is overridden. If this pin is
  used the logic state of the pin is unchanged but
  the information is stored in an internal latch.
  After the DDRD retains control of the bit the
  information will be loaded.
• Transmitter Enabled
• Bit 1 of DDRD is overridden.

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Wake Up

• Software in the receiver evaluates if the data is
  intended to a receiver.
• Reduces the service of SCI in multiple receiver
  systems.
• Two methods
• Idle Line wake up as soon as RxD line becomes
  idle. All devices are awake (RWU0) until they
  realize that the message is not intended for
  ?RWU1. Then wake up when a idle line of 10 RxD
  is detected.
• Note 1 bit time between idle and message and no
  space in message.
• Address-Mark the most significant bit use to
  indicate if is data(0) or address(1) ?all dormant
  receivers wake up if one is detected. Check if
  message is for them.
• Note no idle between messages and space in
  message ok.

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Send Breaks

• Break characters are character length periods
  when the TxD line goes to 0.
• Either 10 or 11 0s.
• As long as the SBK bit is set, break characters
  will be sent.
• After the SBK is set to 0, at least one bit time
  of logic ones appears on the TxD.

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SCI Transmitting and Receiving with the HC11
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Transmitter Block Diagram
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Transmitting Process How to make it work

• Pin 21 (PD1) is the transmitting pin
• Software Runs everything
• 1. Set Baud rate to equal receiver
• 2. Set TE (SCCR2) high to enable
• 3. Set Wake Up mode (SCCR1)
• 4. TE sends idle character to wake receiver
• 5. Receiver determines if message is intended for
  it

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Transmitting Process How to make it work

• Continued
• 6. Load character into SCI Data Register (SCDR)
• 7. Character placed in shift register and shifted
  out
• 8. When TDRE (SCSR) sets back to 1, load another
  character (both polling and interrupts can be
  used).
• 9. Transmission complete (TC in SCSR)
• 10. Idle line rests at logic 1, RWU goes to 0

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Transmitter Interrupts

• 2 Interrupts for Transmitter
• TIE (SCCR2) associated with TDRE
• TCIE(SCCR2) associated with TC
• Set to 1 to enable each in SCCR2
• One Interrupt Vector for SCI System

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Receiving Process How to Make it Work

• Synchronizes SCI internal (RT) clock with data
  stream
• Recovers data characters
• RT runs at 16 times the baud rate
• Receives start bit, followed by 8 or 9 data bits,
  and then a stop bit
• Start bit is always 0 and stop bit is always 1

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Receiver Block Diagram
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Finding the Start Bit

• First look for pattern 1110
• RT clock incremented to RT2
• Take samples at RT3, RT5, and RT7 if two of them
  are 1 noise is assumed and the start bit is
  ignored

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Reading a Bit of Serial Data

• Receiver Circuitry Clocks the Input (RT Clock) at
  a rate 16 x the Baud Rate
• Each Bit is Sampled at 3 RT time intervals, 8RT,
  9RT, 10RT
• Majority of 3 Readings Value of the Bit

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Detecting Noise (Case 1)

• Noise causes start bit to be detected too soon
• RT5 and RT7 are 0, so start will be accepted
• RT3 is 1, so noise flag will be set

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Detecting Noise (Case 2)

• Start bit is found correctly
• Start accepted because RT3, RT5 and RT7 are 0
• RT8 and RT10 are 1, so noise flag will be set,
  but bit sense is still 0, because it is start bit

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Framing Errors

• If there has been a framing error without
  detection of a break, the start edge is
  artificially placed and the circuit continues to
  operate

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SCI Robustness

• In 8 bit format the transmitter and receiver baud
  rates can vary by 4.5 and in 9 bit format they
  can vary by 4
• Reads are doubled buffered one character is in
  the SCDR while the other is being shifted in the
  receive serial register
• RT clock can be resynchronized on a valid 1 to 0
  transition within a frame.

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Wake Up Feature

• In multi-receiver systems, SCI service overhead
  can be reduced by putting receiver to sleep when
  incoming data is not meant for it.

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Wake Up Feature

• Two Methods
• Idle Line Wakes up when RxD line becomes idle
  (continuous logic high for 10-11 full bits)
• with this method, no idle time is permitted
  within a message, and there must be idle time
  between messages
• Address Mark MSB in a character indicates if the
  character is an address(1) or data(0) and the
  receiver wakes up for an address
• no idle time restrictions
• an extra bit must be transmitted for each
  character

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Configuring the Receiver

• Set Baud rate in Baud register (102B)
• Set bit 4 in SCCR1 (102C) to select 8 or 9 bit
  characters set bit 3 to select wake up mode
• Set bit 2 in SCCR2 (102D) to enable receiver
  set bit 4 to enable interrupt on idle set bit 5
  to enable interrupt when character received or
  overrun occurs.

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Using the Receiver

• Read status of receive from SCSR (102E) Bit 5
  will be set when data is received framing error
  sets bit 1 noise sets bit 2 overrun sets bit 3
  idle sets bit 4
• Read data received from SCDR (102F)
• If 9 bit data format is used, the ninth bit of
  data will be located in bit 7 of SCCR1 (102C)

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References

• HC11 Reference Manual
• HC11 Technical Data
• Bishop, Basic Microprocessors and the 6800