PLD

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PLD

• Xilinx CoolRunner

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reference

• CoolRunner/CoolRunner-II datasheet
• Application Note
• 5V Tolerance Techniques for CoolRunner-II
  Devices, XAPP429

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Xilinx CPLDs Low Cost Solutions At All Voltages
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CPLD Product Portfolio

• 3.3V core
• 2.7V - 5V I/O
• LVCMOS, LVTTL
• Low power
• Fast Zero Power

• 1.8V core
• 1.5V - 3.3V I/O
• SSTL, HSTL, LVCMOS, LVTTL
• Lower power
• DataGATE
• Clocking features
• Clock Divide
• CoolCLOCK
• DualEDGE

• 2.5V core
• 1.8V - 3.3V I/O
• LVCMOS, LVTTL
• I/O Banking

• 3.3V core
• 2.5V - 5.0V I/O
• LVCMOS, LVTTL

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One Ultimate CPLD Solution for All Designs
Lowest Power 28µW 16µA typical stand-by
Low Cost 0.18µ small die size Lowest cost
packaging
High Performance 3.0ns TPD, FMAX 385Mhz Improved
features
Storage Systems, Routers
Set-Top Box, Cell phone
Handheld, Portable Equipment
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CRII

• Processe lower cost FZP 0.18µ design
• High performance, 1.8 volt, 100 digital core, up
  to 385MHz
• Ultra low power, industry lowest dynamic static
  ratings
• Product feature rich, complete product offering
• Multiple I/O standards with input signal
  hysteresis
• Advanced system timing features
• Clock doubler for gt 500MHz Ftoggle rate
• Clock divider for lower power
• Even lower power consumption with CoolCLOCK
  DataGATE
• 32 to 512 macrocell densities with optimized
  packaging

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Key Features

• RealDigital design methodology
• Total CMOS PLDs,
• 180nm, 1.8V, digital core
• 3.0ns TPD, 385MHz FMAX (32mc device)
• I/O
• HSTL, SSTL, LVTTL, LVCMOS
• Multiple I/O banking on larger devices
• Input port with Hysteresis function
• Clocking
• DualEDGE FlipFlop
• Clock Divider and CoolCLOCK
• Low power
• 28.8µW at 1.8V, even lower power possible with
  DataGATE

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The RealDigital CPLD Advantage
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CRII Architecture
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Function Block
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Macrocell Architecture
Control Termsclocking (CTC), asynchronous set
(CTS), asynchronous reset (CTR), output enable
(CTE)
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PAL PLA
XPLA3 use PLA (full connected OR matrix)
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PAL PLA (contd.)
??????????,????????,????
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Function of Flip Flop (1)
D-FF
T-FF
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Function of Flip Flop (2)
Latch
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DualEDGE triggered registers
process (clock) begin if (clockevent) then
... end if end process

• double system performance

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I/O Block Architecture
500 mV of hysteresis will be added
when Schmitt-trigger inputs are selected.
??????????
For HSTL/SSTL
???????/??????
Outputs can be directly driven, 3-stated or
open-drain configured. slow or fast slew rate
output signal is selectable
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Slew Rate Control
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Input Hysteresis

• All I/O pins support input hysteresis
• Increase separation of true versus false levels
• Enabled on a per-pin basis
• Ideal for slow edge rate,noisy signalsnoise
  immunity
• Analog comparators sensors
• Hall effect switches
• IR input
• R/C oscillators / crystals
• Reduces power consumption by eliminating false
  switching
• Reduces cost by eliminating external Schmitt
  trigger buffers

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Schmitt Trigger
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Schmitt Trigger (contd.)
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Schmitt trigger input vs. saving power

• When input signal have low noise and fast rise
  time edge, disable schmitt trigger
• When input signal have slow rise time
  edge,enabling schmitt triggernormal input buffer
  will consume more power during the transition.

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Bus Holder
Bus hold??I/O ?????,???????????CRII???????I/O
pin??????????????????????,????????,????????,??????
????????????
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IO Standard
output pins are grouped in large banks to support
different IO standard at the same time
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OD Gate
????????
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DataGATE
???? ???? ?????
????????
???
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Additional Clock Options

• Division
• Division by 2,3,4,8,10,12,14,16
• DualEDGE
• Each macrocell has the ability to double its
  input clock switching frequency.
• CoolCLOCK
• For additional power savings,by combining the
  clock division circuitry with the DualEDGE
  circuitry

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CoolCLOCK
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Design Security

• Designs can be secured during programming to
  preventeither accidental overwriting or pattern
  theft via readback
• Four independent levels of security
• These security bits can be reset only by erasing
  the entire device

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Timing Model (1)
a fast path into the macrocel
represents one aspect of the overall architecture
from a timing viewpoint. Each little block is a
time delay that a signal will incur if the signal
passes through such a resource.
Fold-back NAND path
Fast input path to each macrocell if used as an
Input Register
universal control terms
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Timing Model (2)
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Timing Model (3)
?????????
???2-56?????????
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Timing Model (4)
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Timing Model (5)
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Timing Model (6)
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Timing Model (7)
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Timing Model (8)
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Timing Model (9)
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Power Saving techniques

• ICdV/dt
• ICdV 1/dt
• ICdV f
• dVv2-v1V-0V
• IC V f
• PI VC V2 f
• PTotalPstatic C V2 f

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Power Saving techniques

• FReduce system speed, average toggle rate
• Avoid input floating to turn off one of the 2
  transistors (P and N channals)
• Increase input edge speed to avoid input spends
  more time biased in the linear region.
• Eliminate bus conflicts caused by two output
  buffers driving a line at the same time in
  opposite directions.
• Weak pull-up 10k,the larger the less power
  consumed but slower bus response time
• Recommend bus hold circuit, remove pull-up.exept
  special circuit like I2C SDA line.

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Power Saving techniques

• Bus terminations
• Pull-down resistors reduce reflections in high
  speed designs
• valuetransmission lines impedance, positioned
  as close to the load pin as possible. Consume
  more power.
• Avoid using it by using a very short
  transmission line
• Or insert a series termination resistor
  positioned at the source pin valuetransmission
  lines impedance. But it will allow one
  reflection at the load.
• Reduce system voltage
• Reduce bus loading
• Capacitive bus component lumped-gateof
  inputbuffer of other CMOS devices
  /distributed-routingof the trace on the PCB
• Resistive bus component

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Design Example (Shifter)
Normal Shifter
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Design Example (DDR Shifter)
DDR Shifter
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Design Example (Counter)
Counter
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5V Tolerance Techniques forCoolRunner-II Devices

• a thick gate oxide provides a high amount of
  voltage tolerance, but sacrifices speed and
  threshold levels. A thin gate oxide makes for a
  faster transistor, but the overvoltage tolerance
  is poor
• CR II thickness 70 Angstroms. This results in an
  "absolute" limit of about 4.2V.
• The CoolRunner-II data sheet lists the absolute
  maximum input voltage as 4.0V.

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5V ? CRII (1)
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5V ? CRII (2)
1n1418 capacitance 4pf, forward voltage 1V,
recovery 4ns
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5V ? CRII (3)
For any particular diode, an increase in
resistance value will result in slower edge
transition, and lower power consumption. The
converse also applies a lower value resistor
will result in faster edges, but more power is
consumed
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5V ? CRII (4)
Diode factors capacitance /forward voltage/
switching characteristics 2pf, switching speed
of 1ns. (faster than the 1n4148)
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5V ? CRII (5)
n-channel MOSFET Benefit not dissipating any
power in a termination resistor.
The voltage at the pin of the CPLD is determined
by the value of the termination voltage minus the
threshold voltage.
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Applications

• Demo Board
• MP3 Player
• CR 2 8051 Interface
• Logic Analyzer

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Demo Board
Fruit Battery
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MP3 Player
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CR 2 8051 Interface (1)
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CR 2 8051 Interface (2)
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Logic Analyzer