Interrupts and Resets

1
Interrupts and Resets

• Crystal Hsu
• Daniel Folkers
• Jared Lee
• ME 6405 Introduction to Mechatronics
• October 22, 2002

2
Outline

• Introduction to interrupts
• Non-maskable and maskable interrupts
• Vectors
• Interrupt Flow
• Standby Modes
• Resets
• Applications

3
Polling

• Loop to continuously read inputs and update
  outputs
• Disadvantages
• Inefficient method since microprocessor uses a
  lot of time polling data lines.
• May miss data if intervals between checking data
  lines are too long

4
Interrupts

• Peripheral issues an interrupt request when it
  has to transfer data to microprocessor.
• Temporarily suspends execution of main program,
  while microprocessor jumps to service routine for
  the peripheral
• Disadvantages requires more complex hardware and
  software.

5
Interrupt Process

• Peripheral activates interrupt request line to
  microprocessor
• Microprocessor finishes execution of current
  instruction
• Contents of registers loaded into stack to allow
  Interrupt Service Routine (ISR) to use registers

6
Interrupts Stacking Order
7
Interrupts RTI

• ReTurn from Interrupt last instruction of every
  ISR.
• Pulls saved registers off stack in reverse order.
• Causes processing to resume where it was
  interrupted

8
Interrupt Types

• Non-maskable
• 6
• Can always interrupt program execution
• Maskable
• 15
• Can be enabled/disabled by mask bits

9
Non-maskable Interrupts

• Priority
• RESET pin
• Clock monitor reset
• COP watchdog reset
• XIRQ interrupt
• Illegal opcode interrupt
• Software interrupt (SWI)

10
XIRQ Interrupt

• Input pin that provides a way of requesting a
  non-maskable interrupt after reset initialization
• When X mask bit in CCR is set, disables XIRQ

11
XIRQ Interrupt X bit

• X bit set by hardware only
• After any reset
• When XIRQ interrupt recognized
• X bit cleared by software only
• TAP (transfer accum A to CCR) instruction
• RTI instruction

12
Illegal Opcode Interrupt

• When an illegal opcode is detected, interrupt is
  requested to illegal opcode vector
• When interrupt service finished, stack pointer
  should be reinitialized to prevent repeated
  execution of illegal opcode
• If uninitialized, illegal opcode vector could
  point to illegal opccode causing infinite loop

13
Software Interrupt (SWI)

• SWI executed in same manner as any other software
  instruction
• Not inhibited by global interrupt mask bits (X
  and I) in CCR
• Similar to maskable interrupts
• Sets I bit in CCR
• CPU registers stacked

14
Maskable Interrupts

• Priority
• IRQ
• Real time interrupt
• Timer input capture 1-3
• Timer output compare 1-4
• Timer input capture 4/output compare 5
• Timer overflow
• Pulse accumulator overflow
• Pulse accumulator input edge
• SP transfer complete
• SCI system

15
Maskable Interrupts

• Most interrupts are maskable
• Masking an interrupt prevents its execution
• All maskable interrupts disabled if set I bit 1
  in CCR
• Many maskable interrupts require flags to be set

16
Maskable Interrupt Priority

• Highest PRIOrity Interrupt Register (HPRIO) can
  elevate priority of one of maskable interrupts
• Use PSEL bits (0-3) of HPRIO register to assign
  highest priority to a maskable interrupt
• Can be set at any time during program as long as
  I bit is set

17
HPRIO
18
Maskable Interrupts I bit

• When set, interrupts become pending but will not
  be executed
• When cleared, interrupts enabled to interrupt
  normal program flow when requested

19
Setting the I bit

• Set during RESET to allow minimum system
  initialization
• Set upon entry to any ISR
• Can be set by software to prevent execution of
  maskable interrupts
• SEI (SEt Interrupt mask)

20
Clearing the I bit

• Can be cleared by software instruction
• CLI (CLear Interrupt mask)
• Automatically cleared by RTI instruction

21
Vectors

• Vectored means there is a specific space in
  memory associated with the interrupt sources.
• This space contains the the address where the
  next instruction to be executed is located.

• In other words, interrupt vectors contain the
  starting address of the interrupt service routine.

22
Interrupt Vectoring Example

• Loading PC with starting address of Timer
  Overflow service routine after a Timer Overflow
  interrupt is triggered. (This vector is not valid
  for systems using the EVBU.)

23
Enabling Interrupts

• Interrupts must first be enabled globally and
  then locally
• Global Masks (I and X bits)
• I-bit can be changed as many times as necessary
• X-bit cannot be reset after first clearing since
  reset

• Local Masks (depend on interrupt source)
• Local masks differ from global masks by the fact
  that CLEARING it DISABLES the respective
  interrupt.

24
Disabling Interrupts

• Interrupts can be disabled by the user or
  automatically by the system
• The user can do so by using the SEI command
  thereby masking all maskable interrupts as many
  times as desired.
• They are disabled automatically when an interrupt
  is issued and re-enabled by the RTI instruction
  at the end of an interrupt service routine.

25
Nested Interrupts

• A nested interrupt is one that is performed
  within an interrupt service routine.
• They are accomplished by masking the present
  interrupt with a local enable mask bit or
  clearing the interrupt source flag before
  clearing I-bit within the current ISR.
• An infinite loop will occur if done executed
  properly.

26
Nested Interrupts

• Nested interrupts are discouraged by Motorola due
  to system complication and the rarity of
  performance enhancement.

27
Interrupt Requests

• Interrupts are requested when an interrupt driven
  event is triggered such as the SWI instruction or
  a low-level signal is applied to the external IRQ
  pin.
• ALMOST all interrupt sources have a local flag as
  an indicator.
• If that interrupt is enabled, it is said to be
  pending.

28
Entering Interrupt Service

• Current instruction finishes execution
• CPU registers are pushed onto the stack
• I-bit is set (and X-bit if XIRQ interrupt is
  requested
• Interrupt vector is fetched
• CPU branches to ISR

29
The Three Basic Steps to Exiting an Interrupt
Service

• Clear the local flag for the interrupt being
  serviced before exiting the ISR.
• Do not clear the I-bit or otherwise unmask the
  interrupt before leaving the ISR (unless you want
  to do a nested interrupt, which is not wise
  anyhow).
• Use the RTI instruction to exit the ISR NOT RTS.

30
Interrupt Flow Chart
31
Standby Modes

• Purpose To reduce power consumption without
  complete system shutdown.
• Mode Types
• Wait Mode
• Stop Mode

32
Wait Mode

• Initiated by the WAI instruction.
• While in wait mode, the address/data bus
  repeatedly runs read cycles to the address where
  the CCR contents were stacked.
• Saves power by suspending processing until an
  external IRQ, an XIRQ, or an internally generated
  interrupt is detected.

33
Wait Mode

• Level of power reduction depends on number of
  internal clocks that can be shut down
• Extra steps can be taken to minimize power
  consumption by performing the following tasks
• Disabling the free-running timer by setting the I
  and NOCOP bits to 1
• Powering down the A/D converter by setting the
  ADPU bit to 0
• Disabling the SPI system, SCI receiver and SCI
  transmitter with their respective control bits.

34
Stop Mode

• Reduces power consumption to a bare minimum by
  shutting down all internal clocks including the
  crystal oscillator
• As long as VDD power is maintained, CPU and I/O
  pin levels are static and unchanged
• Initialized by STOP instruction while both S-bit
  in CCR and CME-bit in the OPTION register are set
  to 0

35
Stop Mode

• If STOP instruction is used when S-bit is set to
  1, it is treated as a NOP instruction
• If STOP instruction is used when CME-bit is 1, it
  acts as a software initiated reset
• Stop mode is exited by applying a low level logic
  to IRQ, XIRQ, or RESET or by a pending edge
  triggered IRQ

36
Things to Keep in Mind When Exiting Stop Mode

• Using IRQ
• To use the IRQ exit method, the I-bit in the CCR
  must be clear (i.e. IRQ not masked)

• Using XIRQ
• Can be used regardless of state of X-bit though
  recovery method is affected
• If X-bit is set to 0 the MCU starts up and
  performs the XIRQ request
• If X-bit is set to 1 processing continues with
  the instruction following the STOP instruction

37
Things to Keep in Mind When Exiting Stop Mode

• Using RESET
• Normal reset sequence occurs in which all I/O
  pins and functions are restored to their initial
  states, but may have some adverse effects if
  caution is not taken

38
Things to Keep in Mind When Exiting Stop Mode

• Since the oscillator is stopped, a restart delay
  is required if an external oscillator is not
  being used
• If an external oscillator is used, the DLY
  control bit can be used to bypass the startup
  delay
• Since RESET sets the DLY control bit to 1, it
  should not be used as the recovery method if you
  want to bypass the startup delay

39
Resets

• Introduction
• Initial conditions established by reset
• Causes of reset
• Applications of resets and interrupts

40
Introduction to Resets

• Similar to interrupts except for they dont save
  states
• Use similar concept of vector fetching
• Forces MCU to reset and assume a standard set of
  initial conditions
• Initializes state of system by initializing SP
  and control registers
• Begins running software from a predetermined
  starting address

41
Initial Conditions

• Central Processor Unit (CPU)
• CPU fetches start vector from locations
  FFFE,FFFF or other depending on mode and type of
  reset
• Stack pointer and other registers are
  indeterminate immediately after reset
• X and I interrupt mask bits in the CCR are set to
  mask any interrupt request
• S bit in the CCR is set to disable stop mode

42
Initial Conditions

• Memory Map
• RAM and I/O (INIT) register initialized to 01,
  placing 256 bytes of RAM at locations 0000-00FF
  and the condition control registers at locations
  1000-103F
• 8-kbyte ROM and 512-byte EEPROM may or may not be
  present

43
Initial Conditions

• Parallel I/O
• In expanded/multiplexed mode the 18 pins used for
  handshake I/O are dedicated to the expansion bus
• In single-chip mode the strobe A flag (STAF),
  strobe A interrupt (STAI), and handshake (HNDS)
  control bits in the parallel I/O control (PIOC)
  register are cleared so no interrupts are pending
  or enabled
• Single strobed mode is selected.

44
Initial Conditions

• Parallel I/O continued
• Port C is initialized for input
• Port B is an output port with all bits cleared

45
Initial Conditions

• Timer
• Timer is initialized to a count of 0000
• Prescaler bits are cleared and output-compare
  registers are set to FFFF
• Input-capture registers are indeterminate
• All nine timer interrupts are disabled

46
Initial Conditions

• Real-Time Interrupt
• Real-time interrupt flag is cleared
• Automatic hardware interrupts are masked
• Rate control bits are cleared and may be
  initialized by software
• Pulse Accumulator
• System is disabled and pulse accumulator input
  (PAI) defaults to general-purpose input pin

47
Initial Conditions

• Computer Operating Properly (COP) Watchdog
• System is enabled if NOCOP control bit in CONFIG
  register (EEPROM cell) is clear and disabled if
  NOCOP is set
• COP rate is set to shortest duration timeout
• Serial Communications Interface (SCI)
• SCI baud rate is indeterminate
• Transmit and receive interrupts are masked and
  transmitter and receiver are disabled
• Port pins become general I/O lines

48
Initial Conditions

• Serial Peripheral Interface (SPI)
• System is disabled by reset and the port pins
  become general I/O
• Analog-to-Digital (A/D) Converter
• System is indeterminate and conversion complete
  flag is cleared
• A/D power-up (ADPU) bit is cleared, disabling the
  A/D system

49
Additional Consequences

• CONFIG register
• Uses EEPROM-based register
• Selects options automatically on power-up or
  reset
• Enables/disables COP watchdog timer
• Mode of operation
• Single-chip/expanded mode etc.

50
Additional Consequences

• Program counter loaded with reset vector
• Vector points to first instruction of users
  program
• Vector location depends on cause of reset and
  mode of operation

51
Causes of Reset

• Power-On Reset (POR)
• COP Watchdog Timer Reset
• Clock Monitor Reset
• External Reset

52
Causes of Reset

• Power-On Reset (POR)
• Initializes internal MCU circuits as Vdd is
  applied
• Reset pin held low for 4064 cycles of internal
  PH2 clock
• Time delay allows oscillator to reach stable
  operating frequency

53
Causes of Reset

• COP Watchdog timer reset
• Occurs when watchdog times out
• Detects software errors
• Software must clear watchdog timer
• COP timeout period is set by the COP timer rate
  control bits (CR1 and CR0) in the OPTION register
  (both 0 after reset)
• MCU internal E clock divided by 215 before
  entering COP system

54
Causes of Reset

• COP Watchdog timer reset
• Software COP is a two step process
• Write 55 to the COPRST register to arm the COP
  timer-clearing mechanism
• Write AA to the COPRST register, which clears
  COP timer
• Clock Monitor Reset
• Monitors E-clock frequency and resets if it is
  too low (lt10kHz)
• Egt200kHz will prevent clock monitor errors

55
Causes of Reset

• Clock monitor reset
• Enabled by setting CME control bit
• Circuit based on an internal RC time delay
• Used as a backup for the COP watchdog system
• Also protects against the unintentional execution
  of the STOP instruction

56
Causes of Resets

• External Reset
• Caused by applying low level signal to the RESET
  pin
• Reset pin is held low for four cycles
• Pin is sampled 2 clock cycles later
• If still low external reset assumed
• Else reset source is assumed to be internal (COP
  watchdog or clock monitor timer)

57
Causes of Reset

• External Reset
• Pin should be held low while Vdd is below minimum
  operating level to protect EEPROM from corruption
• Minimum level should exceed 4.6V to avoid
  accidental overwriting of EEPROM

58
Applications of Resets and Interrupts

• I/O data transfers to peripheral devices
• Emergency shutdowns (power-down)
• Power failure (RC circuit senses)
• Reset button on home devices
• Input capture of optical encoder for controlling
  DC motor
• Compiler recognizes an error