Design of 8 Bit ALU

1
Design of 8- Bit ALU

• Neelam Chaudhari
• Archana Mulukutla
• Namita Mittal
• Madhumita Sanyal
• Advisor Dr. David Parent
• Date May 8, 2006

2
Agenda

• Abstract
• Introduction
• Why
• Theory behind.
• Back Ground information (Lit. Review)
• Summary of Results
• Project (Experimental) Details
• Results
• Cost Analysis
• Conclusions

3
Abstract

• We designed 8- bit ALU using Kogge Stone
• Tree Adder.
• Specifications
• Frequency 200MHz
• Area 631 850 Sq.um
• Power 0.2mW
• Functionality
• Logical operations A AND B, A XOR B
• Arithmetic Operations AB

4
Kogge Stone Adder.
(retrieved from http//odin.ac.hmc.edu/harris/cla
ss/e158/lect11.ppt284,36,Kogge-Stone)
5
Block Diagram
AOI 3333 Propagate Generate Block
CARRY NETWORK
G
SUM GENERATOR
P
AOI 333 3 1 MUX
Output
6
Introduction

• Why this Project?
• ALU is Basic Building Block of several circuits.
• Challenging to implement CLA with least number of
  logic levels and fan-ins.
• Look ahead across the look-ahead carry tree.
• Gives us a hands-on design experience on the
  concepts learnt in EE166.

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Schematic
Longest Path
8
Longest Path Calculations
Propagation delay/ Logic level 5ns/16
Note All widths are in microns and capacitances
in fF
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Logic VerificationSum
Arithmetic Operation (AB) A
10101111 B 10000101 00110100
1
Cout
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Logic Verification (contd.)XOR

• Logical Function A XOR B
• A? 10101001
• B? 10000000
• 00101001

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Layout
DRC Verified
12
Layout verification
13
Test Bench
14
Simulations
15
Cost Analysis

• Time spent on each phase of the project
• Verifying logic - 3 Weeks
• Verifying timing - 2 Weeks
• Layout - 4 Weeks
• Post Extracted Timing - 2 days

16
Lessons Learnt

• Planning is very important.
• Start early and have clear estimation of the work
  to be done.
• Give more time for the layout stage.

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Summary

• Designed and tested almost all the design units
  learnt in the class.
• This design can be modified to be used in higher
  order bit ALUs and more functions.
• We designed 8-Bit ALU working at 200 MHz speed
  ,driving 20fF load.

18
Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
  and Remote Login.
• Thanks to Hummingbird for remote login.
• Thanks to Professor David Parent for his valuable
  guidance.