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EMC of IC modeling with IC-EMC Basic concepts
Alexandre Boyer Senior lecturer
September 2009
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IC-EMC software

• Illustrate EMC of ICs notions through different
  problems.
• Solving these problems with the assistance of the
  software IC-EMC.

IC-EMC is a friendly and free PC tool developped
at INSA de Toulouse for modeling and simulating
EMC at IC level. The tool is linked with the
freeware WinSPICE derived from SPICE Berkeley for
analog simulation. Download IC-EMC and WinSPICE
at
http//www.ic-emc.org
Version used in 2009 version 2.0.21
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IC-EMC main screen
IC-EMC simulation tools
Simulation command
Symbol palette
Schematic capture interface
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Simulation flow with IC-EMC
IC-EMC model libraries
IC-EMC schematic Editor (.sch)
WinSPICE compatible netlist generation (.cir)
WinSPICE simulation
IC-EMC Post-processing tools (emission,
impedance, S-parameters, immunity)
Measurement result files import
Output file generation
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Most important icons
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SPICE simulation

• WinSPICE interface
• Click File/Open to open a circuit netlist (.cir)
  generated by ic-emc.
• When the netlist is opened, each time the netlist
  is regenerated, a simulation is launched again.
• Main simulation commands for IC-EMC

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Exercise 1 FFT of trapezoidal signal

• Simulate the FFT of the following signals and
  comment the results.
• 50 duty cycle trapezoidal signal V0 0V, V1
  5 V, Tr Tf 1 ns, PW 49 ns, Period 100ns
• 10 duty cycle trapezoidal signal V0 0V, V1
  5 V, Tr Tf 1 ns, PW 9 ns, Period 100ns.

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Exercise 2 Passive component model
The impedance of two ceramic capacitors has been
measured with a vector network analyzer. The
measurement results are available in the file
basic\impedance\ Zin_Capa47pCeram.z.

• What is the nature of this passive device?
• Propose electrical models for these passive
  devices.
• Explain the physical origin of the electrical
  elements of the model.

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Exercise 3 Microstrip modeling

• Lets consider the coplanar waveguide designed on
  a PCB with the following characteristics
• Substrate FR4
• Width w 0.508 mm
• Gap g 0.254 mm
• Metal thickness t 35 µm
• Substrate thickness h 1.6 mm
• Line length l 50 mm

g
w
t
h

• Propose two electrical models, valid up to 3 GHz
  at least. Compare their full two port S
  parameters profile.
• Load the output of both models by 50 ohms load
  and connect square signal generator at the input.
  Compare the voltage across the load with both
  models with
• F 5 MHz, PW 100 ns, Tr Tf 10 ns
• F 500 MHz, PW 1 ns, Tr Tf 0.1 ns

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Exercise 4 Simultaneous switching noise

• Lets consider the case of the following single
  output buffer. It is modelled as a CMOS inverter
  with the given dimensions. Models of MOS
  transistors are included in the file
  lib/SPICE.lib. This buffer is driven by a
  predriver stage that we model as a square
  generator with the following characteristics
• V0 0 V, V1 5 V
• Tr Tf 1 ns
• Period 100 ns
• PW Period Tr (to keep a 50 duty cycle)
• The output buffer will be loaded with a
  capacitance. The conducted noise on supply lines
  will be probed with a 1 O resistor placed on Vss
  path of the buffer.

• Build the schematic of the I/O loaded by 10 pF.
  Observe the transient response across the 1 O
  probe. Comment. Deduce the amplitude of dynamic
  consumption of current.
• Load the output of the buffer with different
  values of capacitance (from 10 fF to 1 nF).
  Observe the transient response of voltage across
  the 1 O probe and comment.

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Exercise 4 Simultaneous switching noise

• Load the output with a 47 pF capacitor. Plot the
  FFT of the voltage across Vss. What is the
  bandwidth of the noise ?
• Do the simulation of question 3 for Tr 5 ns.
  Comment the result.
• The load is connected to the buffer through a 4
  cm long, 0.5 mm wide tracks drawn on a 1.6 mm FR4
  PCB. Inductance of the package is estimated about
  6 nH. Observe the transient response and the
  spectrum of voltage across the 1 O probe and
  comment.
• Inductance on power supply and ground reference
  are estimated at 10 nH (PCB planes and package).
  Does it influence the power integrity?
• Simulate the noise on ground reference for a 8
  I/O port. Propose a solution to reduce the noise
  amplitude.

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Exercise 5 Power transfer
Lets consider a voltage source with a 50 ohm
output resistance.

• Connect a resistive load at the output of the
  voltage generator. Compute the power delivered to
  the load for different values of resistor. What
  is the condition to optimize the power transfer
  to the load ?
• The maximum power transferred to the load is
  called maximum available power. Give an
  analytical expression of the maximum available
  power.
• RF generator gives amplitude in term of power.
  What is this power ?
• Connect a directional coupler between the
  generator and the resistive load. Compute the
  forward and reflected power, and the power
  transferred to the load for Rload 10, 50 and
  100 ohms. What is the relation between the three
  power values ? What is the relation between
  reflected and forward power ?
• For which condition the voltage across the load
  is maximum ?
• In the case of a 50 ohm load, what is the
  required forward power to induce a voltage of 1 V
  across the load ? Confirm this value by a
  susceptibility simulation (simulate the
  susceptibility threshold between 10 and 100 MHz).
• And in the case of a 10 ohm load ? And a 100 ohm
  load ?