chapter four transparency

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Chapter 5 Operation Modes and Memory Expansion
The 68HC11 Microcontroller
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The 68HC11 Operation Modes - Single chip mode a
mode in which the 68HC11 functions without
external address and data buses. The 68HC11 has
5 I/O ports (A, B, C, D, and E) to use in this
mode. - Expanded mode a mode in which the 68HC11
has the capability to access a 64KB address
space. In this mode, port B is used as the upper
address signals (A15-A8) and port C is used as
time-multiplexed address/data bus (A7/D7-A0/D0).
Only three I/O ports are available for direct
use. - Special test mode a mode which is mainly
used by Motorola in fabrication
testing. - Special Bootstrap mode a mode in
which a bootstrap ROM is enabled. The
bootstrap ROM contains a loader program that
will be executed after the RESET signal is going
high and this program will load in a 256-byte
program from the SCI subsystem to the on-chip
SRAM and then transfer the CPU control to that
loaded program. Establishment of the operation
mode On the rising edge of the RESET, the
voltage levels on pins MODA and MODB are
latched into the HPRIO register, which determines
the operation mode of the 68HC11.
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Memory Technologies and Terminology 1. Nonvolatil
e and volatile memories differentiated by the
fact if a memory component will lose its
contents when the power is removed. 2. ROMs and
RAMs differentiated by the fact if a memory
component can be read/write from/into for
roughly the same amount of time. 3. Dynamic and
Static RAMs differentiated by the fact if a RAM
requires periodic refresh operation in order to
maintain its stored information. 4. Memory
capacity refers to the total number of bits a
memory chip has. 5. Memory organization
describes the number of bits that can be accessed
from a memory chip in one operation.
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Example 5.1 Using the following memory chips, how
many SRAM chips will be needed to build a 512KB,
16-bit memory system for a 16-bit
microprocessor? a. 256K 1 SRAM b. 256K 4
SRAM c. 256K 8 SRAM d. 64K 8
SRAM Solution a. Sixteen SRAM chips with 1
organization are needed to construct a 16-bit
memory system. 16 256K 1 chips are required
to build a 512KB 16-bit memory system. b. Four
SRAM chips with 4 organization are needed to
construct a 16-bit memory system. Four 256K 4
SRAM chips are needed to construct a 512 KB
16-bit memory system. c. Two SRAM chips with
8 organization are needed to construct a 16-bit
memory system. Two 256K 8 SRAM chips are
needed to construct a 512 KB 16-bit memory
system. d. Two SRAM chips with 8 organization
are needed to construct a 16-bit memory system.
Eight 64K 8 SRAM chips are needed to construct
a 512 KB 16-bit memory system.
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Remapping 68HC11 on-chip SRAM and I/O
registers - The upper four bits of the INIT
register remap the on-chip SRAM to the beginning
of any 4KB page - The lower four bits of the INIT
register remap the I/O registers to the
beginning of any 4KB page. - The remapping of
SRAM and I/O registers can only be done within 64
E clock cycles after reset. Example 5.2 Remap
the 68HC11 on-chip SRAM to 2000-20FF and remap
I/O registers to 3000-303F. Solution To remap
SRAM to 2000-20FF, set the upper four bits of
the INIT register to 2. To remap I/O registers
to 3000-303F, set the lower four bits of the
INIT register to 3. SRAM equ 20 value to
remap SRAM to 2000-20FF IOREG equ 03 value
to remap I/O registers to 3000-303F remap equ S
RAMIOREG INIT equ 1030 ldab remap staa INIT
. .
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• External Memory Expansion Issues
• address space assignment
• address decoding
• timing consideration

Address space assignment - only unallocated
memory space should be assigned to external
memory components - memory space is often
allocated in the unit of 2n KB (n is an integer)
for 8-bit microcontrollers - address decoder
can be simplified if memory space is divided into
blocks of the same size. Allocated space for
the 68HC11A8 0000-00FF SRAM 1000-103F I/O
registers B600-B7FF EEPROM E000-FFFF ROM
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Example 5.3 Assign the 68HC11 memory space using
a block size of 4KB. Solution The 64KB memory
space can be divided into 16 4KB blocks.
Block number Address range
0000-0FFF 1000-1FFF 2000-2FFF 3000-3FFF 4
000-4FFF 5000-5FFF 6000-6FFF 7000-7FFF 800
0-8FFF 9000-9FFF A000-AFFF B000-BFFF C000-
CFFF D000-DFFF E000-EFFF F000-FFFF
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Example 5.4 Assign the 68HC11 memory space using
a block size of 8KB. Solution The 64 KB space
can be divided into eight 8KB blocks.
Block number Address range
0000-1FFF 2000-3FFF 4000-5FFF 6000-7FFF 8
000-9FFF A000-BFFF C000-DFFF E000-FFFF
0 1 2 3 4 5 6 7
Address decoding methods - partial-decoding
each addressable location responds to more than
one address on the system bus - full-decoding
each addressable location responds only to one
specific address on the system bus
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TTL Decoder Chips - 74138 a 3-to-8
decoder - 74139 dual 2-to-4 decoder
74138
74139
E1 E2
O0 O1 O2 O3 O4 O5 O6 O7
1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3
E1 A1 A0
E3
E2 B1 B0
A2
A1
A0
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Example 5.5 Use a full decoding scheme to design
an address decoder for a computer that has the
following address space assignments SRAM1 2000
-3FFF ROM1 4000-5FFF E2PROM 6000-7FFF SR
AM2 A000-BFFF ROM2 C000-DFFF Solution
Each memory component is 8KB. A 3-to-8 decoder
74LS138 can be used as the address decoder. The
highest 3 address bits will be used as the
address inputs to the decoder.
The highest three address bits for each component
are SRAM1 001 ROM1 010 E2PROM 011 SRAM2 101
ROM2 110
The decoder circuit is
E1 E2
O0 O1 O2 O3 O4 O5 O6 O7
SRAM1_CS ROM1_CS E2PROM_CS SRAM2_CS ROM2_CS
E3
E
A2
A15 A14 A13
A1
A0
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Example 5.6 Design an address decoder for a
68HC11-based product that has 2KB of external
E2PROM and 2KB of external SRAM using partial
decoding method. Solution - Use the dual
2-to-4 decoder 74139 as the address decoder.
- Divide the 64KB address space of the 68HC11
into four 16 KB blocks. - Use the two highest
address signals A15A14 as the address inputs to
the decoder. - Assign the address space
4000-7FFF to E2PROM. - Assign the address space
8000-BFFF to SRAM.
74139
E1
1Y0
E
E2PROM_CS
1Y1
SRAM_CS
A1
A15
1Y2
A14
A0
1Y3
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Conventions of Timing Diagrams - Ideal signals
have 0 rise and fall times
1
0
Figure 5.4 An ideal signal
- A real signal has nonzero rise and fall times
(textbook definition)
tfall
trise
90VDD
10VDD
Figure 5.5 The diagram of a real signal
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- A single signal is represented as a sequence of
line segments
1
0
Figure 5.6 A single-signal waveform
- Multiple signals of the same nature are
represented as two parallel lines with
crossovers from place to place
1
1
Figure 5.7 A multiple-signal waveform
- Unknown signals (when they changing) are
represented as hatched area
1
0
unknown
(a) single signal
0
(b) multiple signals
0
unknown
Figure 5.8 Unknown signals
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- Floating signals are represented by a value
between high and low
floating
(a) Single signal
floating
(b) Multiple signals
Figure 5.9 Floating Signals
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- There are causal relationships between two or
multiple signals
Cause
Signal A
Result
Signal B
(a) Single cause and single result
Signal A
Causes
Signal B
Signal C
Signal D
Result
(b) Multiple causes and single result
Cause
Signal A
Signal B
Results
Signal C
(c) Single cause and multiple results
Signal A
Causes
Signal B
Signal C
Results
Signal D
Figure 5.10 Signal causal relationships
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The 68HC11 Bus Cycle Timing Diagrams - A 68HC11
external bus cycle can only be performed in
expanded mode and controlled by the E clock
signal. - All read and write bus cycles take one
E clock cycles to complete. - All timing
parameters use 20 and 70 of the power supply
voltage as reference points. (Motorola is using
this convention) - Most timing parameters are
measured relative to the rising and falling edges
of the E clock signal. - The phrase before the
rising edge of the E clock uses the time when the
magnitude of the E clock signal is 0.2VDD as a
reference point. - The phrase after the rising
edge of the E clock uses the time when the
magnitude of the E clock signal is 0.7VDD as a
reference point. - The phrase before the falling
edge of the E clock uses the time when the
magnitude of the E clock signal is 0.7VDD as a
reference point. - The phrase after the falling
edge of the E clock uses the time when the
magnitude of the E clock signal is 0.2VDD as a
reference point.
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tcyc
tf
PWEH
PWEL
E
tr
tAH
R/W
tAV
tAH
tACCA
A15-A8
tAVM
tDHR
tMAD
tDSR
tASL
tACCE
DATA
ADDRESS
A7-D7-A0/D0
tAHL
tr
AS
PWASH
tASD
tASED
Figure 5.11 68HC11 Read Bus Cycle Timing Diagram
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For the 2 MHz E clock signal and the 68HC11 read
bus cycle timing diagram - PWEL is the E clock
low pulse width (227 ns) - PWEH is the E clock
high pulse width (222 ns) - A15-A8 and R/W
signals are valid tAV (94ns) before the rising
edge of E clock - A15-A8 and R/W signal remain
valid for tAH (30 ns) after the falling edge of E
clock - A7-A0 and D7-D0 are multiplexed on the
same PC7-PC0 pins - PC7-PC0 are used as A7-A0
when E clock is low - PC7-PC0 are used as D7-D0
when E clock is high - A7-A0 are valid tAVM (86
ns) before the rising edge of E clock - Read data
must be valid for tDSR (30 ns) before the falling
edge of E clock sot that 68HC11 can read it
correctly - Read data must be valid for tDHR
(0-83ns) after the falling edge of E clock sot
that 68HC11 can read it correctly - The falling
edge of the AS signal is often used by the
address latch to latch A7-A0 and A7-A0 remain
valid for tAHL (26 ns) after AS falls
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Adding an 8KB SRAM HM6264A to the 68HC11 - The
HM6264A has 13 address pins to address each of
the 8192 locations on the chip. - The HM6264A
uses 8 organization. - There are two chip enable
signals one (CS1) is active low, the other (CS2)
is active high. - The active low signals WE
and OE control the data in and out from the chip.
VCC
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NC
1
A12
27
WE
2
CS2
26
A7
3
A8
25
A6
4
A9
24
A5
5
A11
A4
23
6
OE
22
A3
7
A10
A2
21
8
20
CS1
A1
9
19
I/O8
10
A0
I/O7
18
I/O1
11
I/O6
17
I/O2
12
16
I/O3
I/O5
13
VSS
15
I/O4
14
Figure 5.14 HM6264A Pin Assignment
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The HM6264A Timing Diagrams There are four
access times - Address access time (tAA) - CS1
access time (tCO1) - CS2 access time (tCO2) - OE
access time (tOE)
tRC
Address
tAA
tHZ1
tCO1
tLZ1
tHZ2
tCO2
tLZ2
CS2
tOE
tOHZ
tOLZ
Data
tOH
Figure 5.14 HM6264A Read Cycle Timing Diagram
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tWC
Address
tAW
tWR
tCW
tHZ2
tCW
CS2
tWP
t
tDH
tAS
DW
Din
tOW
Figure 5.15 HM6264A Write Cycle Timing Diagram
- Write data must be valid for tDW before WE
goes high and remain valid for at least tDH
after WE goes high - the pulse width of WE must
be at least tWP
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Adding HM6264A-12 to the 2 MHz 68HC11 - Address
space assigned to the HM6264A-12 is
4000-5FFF - The 74F138, having a propagation
delay of 8 ns, is used as the address
decoder - The 74F373, having a propagation delay
of 11.5 ns, is used as the low address
latch - The WE signal is generated by NANDing the
E clock and the inverting copy of R/W. - The NAND
gate has a propagation delay of 15 ns. - The
inverter that is used to invert the R/W signal
has a propagation delay of 15 ns - The circuit
connection is in Figure 4.16 of the next slide
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68HC11
74F138
PB7/A15
A2
PB6/A14
A1
O2
PB5/A13
A0
E
E
3
E
E
2
1
CS1
CS2
WE
R/W
PB4/A12- PB0/A8
A12-A0
OE
AS
HM6264A
LE
O7-O0
AD7-AD0
D7-D0
OE
74F373
I/O8-I/O1
Figure 5.16 Interfacing an 8KB HM6264A to the
68HC11