Synthesis of Custom Processors based on Extensible Platforms

1
Synthesis of Custom Processors based on
Extensible Platforms

• Fei Sun, Srivaths Ravi,
• Anand Raghunathan and Niraj K. Jha
• Dept. of Electrical Engineering
• Princeton University
• NEC Laboratories America, Inc.

2
Outline

• SoC design constraints
• Background
• Previous work in ASIP design
• Xtensa platform
• Manual custom instruction generation procedure
• Automatic custom instruction generation flow
• Experimental results
• Conclusions

3
SoC Design Constraints

• Time to market
• Cost
• Performance
• Power
• Cost-performance trade-off
• Flexibility

4
Comparison of Different Approaches
ASIC ASIP GPP Time to market --
Cost --Performance
--Power
--Cost-performance --Flexibility
--
Very good Good -- Very bad
5
Flexibility vs. Energy Efficiency
6
Previous Work in ASIP Design

• ASIP architectures and overall design
  methodologies
• Huang, 1994, Adams, 1996, Fisher, 1999,
  Kucukcakar, 1999
• Application-specific instruction set selection
• Choi, 1999, Gschwind, 1999, Arnold, 1999
• Low power ASIP design
• Kalambur, 1997, Dougherty, 1999, Ishihara,
  2000, Sami, 2001
• Commercial offerings
• Xtensa, ARCtangent, Jazz, SP-5flex, Carmel

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Xtensa Architecture
TRACE Port
Instruction
JTAG Tap Control
Instruction Memory or Cache Tags
Instruction Address
On Chip Debug
Align and Decode
Interrupt Control
Branch Logic Instruction Fetch
Memory Protection Unit
Processor Interface
Window Register File
Date Memory or Cache Tags
Exception Support
Coprocessor Register File
ALU Address Generation
Processor Controls
Write Buffer
MAC 16
Base ISA Feature
Data Address
Coprocessor Execution Units
Designer Defined Instruction Execution Unit
Configurable Function
Timers 1 to n
Optional Function
Data
Special Function Register Access
Configurable Optional Function
Data Address Watch 0 to n
Extensible
Sourcewww.tensilica.com
Instruction Address Watch 0 to n
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Xtensa Processor Design Flow
Processor Configuration Inputs
Designer-DefinedInstruction Descriptions
Configuration File
Configured GNUC/C Compiler
Configured Processor HDL
Configured GNUAssembler/Disassembler
Configured Instruction SetSimulator/Emulator
Area, Power and Timing Estimation
Application Source Code
Generator Output
Sample Application Data
Internal Database
Design data
Use of Generated Data
Sourcewww.tensilica.com
Optimized Hardware
Optimized Software
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Manual Custom Instruction Generation Procedure
Identify potential new instructions
Profile, read source code
Slow and error-prone
Describe custom instructions
Understand source code
Insert custom instructions
Rewrite source code
Verify functional correctness
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Contributions of Our Work

• Automatic custom instruction selection
• Application program to extensible processors with
  custom instructions
• Features
• Efficient design space search
• Use accurate information from instruction set
  simulator and synthesis
• Bridge the gap between automatic synthesized and
  manually designed architectures

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Automatic Custom Instruction Generation Flow
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Automatic Custom Instruction Generation Flow
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Example Illustration of Template Generation
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Example Illustration of Template Generation
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Example Illustration of Template Generation
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Example Illustration of Template Generation
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Example Illustration of Template Generation
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Key Observations for Pruning

• Higher the weight of the template, higher the
  potential for improvement --- Amdahls law
• Scope for optimization determined by computation
  --- No. of cycles needed for executing the
  template
• Scope for optimization determined by read/write
  ports limitation --- Additional cycles needed for
  extra reading/writing of input/output variables

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Pruning Algorithm

• Ranking criterion
• OriginalTime Fraction of the total execution
  time of the original program spent in the
  template (weight)
• In, Out Number of inputs and outputs of the
  template, respectively
• a, ß Number of inputs/outputs encoded in the
  instruction
• ? No. of cycles needed for executing the
  template
• Higher priority means greater potential for speed
  up

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Template Generation with Pruning
Ranked pool of seed templates
Threshold 0.1
Template set
10.51
7.92
4.05
2.13
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Template Generation with Pruning
Highest priority
Threshold 0.1
Ranked pool of seed templates
12.73
Template set
1.18
16.35
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Template Generation with Pruning
Highest priority
Threshold 0.1
Ranked pool of seed templates
12.73
Template set
16.35
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Template Generation with Pruning
Highest priority
Threshold 0.1
Ranked pool of seed templates
12.73
16.35
Template set
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No. of Templates vs. Threshold Ratio
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Automatic Custom Instruction Generation Flow
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Automatic Custom Instruction Generation Flow
(Contd.)
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Automatic Custom Instruction Generation Flow
(Contd.)
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Custom Instruction Insertion

• Care must be taken to insert custom instructions
  into appropriate places without affecting
  programs functional correctness
• If custom instructions need extra inputs
  (outputs), care must be taken to select
  appropriate variables to write to (read from)
  user-defined registers

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Example Illustration of Custom Instruction
Insertion
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Example Illustration of Custom Instruction
Insertion (Contd.)
....offset t 1for (i0 ilt100 i)
j .... result offset i j....
....offset t 1for (i0 ilt100 i)
j .... result CustomInstr(i,j)
....
WUR(offset,0)
(a) (b)
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Automatic Custom Instruction Generation Flow
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Custom Instruction Combination Selection ---
Problem Statement

• Given a set of non-overlapping custom
  instructions, with each instruction having
  several versions, find a version for each
  instruction such that performance is maximized
  while area is under a certain threshold

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Custom Instruction Combination Selection --- Flow
Chart
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Automatic Custom Instruction Generation Flow
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Experimental Methodology
C Program
Aristotle
Automatic Custom Instruction Generation
Xtensa GNU Profiler
Xtensa TIE Compiler
Modified C program
Synopsys Design Compiler
Cross Compiler
Tensilica Processor Generator
Sente Wattwatcher
ISS
Synopsys Design Compiler
Execution Cycles
Power
Area
Clock Period
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Experimental Results (Contd.)
Average Performance improvement 3.4X Energy
reduction 3.2X Energydelay reduction 12.6X
Area increase 1.8
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Conclusions

• Automatic custom instruction synthesis for ASIPs
• Template generation/selection
• Custom instruction insertion
• Custom instruction combination selection
• Experimental results
• 3.4X average performance improvement
• 12.6X average energydelay reduction