Final exam review

1
Final exam review
Date Dec. 20th Time 10AM-12PM Room B118 Open
book and open notes.
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Coverage
Chapter 1- chapter 11 and Lab
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Overview of Digital system design

• Old ways of designing digital circuits
• PLD, CPLD, FPGA, ASIC
• HDL, VHDL, Verilog

4
VHDL Tutorial

• Entities
• Archetectures
• Simulation

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VHDL elements

• Identifier
• A,b, sum, cout
• Data objects
• signal, variable, file, constant
• Data types
• Std_logic, bit_vector, integer
• Operators
• And, or, not ,-,,/

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VHDL elements
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Behavioral Modeling

• Process
• sequential executed statements
• sensitivity list (hw)
• signal vs variables (hw)
• wait statement
• signal drivers
• transport and inertial delay model
• multiple processes

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Structural Modeling

• Component declaration
• Component instantiate
• Port map()
• Connecting components using signals

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Structural Modeling
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Dataflow Modeling

• Concurrent signal assignment
• Block
• Guarded block
• Multiple drivers
• Resolution function

11
Primitives

• AND, or, not, xor Gates
• D flipflop, Register, Shift register
• Multiplexer, N bit adder
• Counter, comparator
• Decoder(LED), encoder

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Primitives

• Full adder
• Decoder(LED Decoder)
• Counter
• Comparator

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Testbench and Simulation
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A Simple Test Bench
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Testbench and Simulation
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Generics
Generic map()
L

R
R
R
R
R
R
R
R
R
MB bits
E
E
E
E
E
E
E
E
E
G

G

G

G

G

G

G

G

G


h
h
h
h
h
h
h
h
h
0
1
2
3
4
5
6
7
8









1
2
1
3
1
4
5
1
1
1
1
1
MB bits

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Subprograms and Overloading
Functions Procedures
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The lab example
Using Bit_vector
Using integer
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Subprogram overloading

• Distinguish between overloaded subprograms
• subprogram name
• number of actuals
• types and order of actuals
• names of formal prameters(if named association
  is used)
• result type(for fucntion)

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Generate Statement
For generate If generate
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Aliases
15
8
5
4
3
0
DATA_BUS
RESET
STATUS
RX_READY
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Attribute
Value attributes'left 'right 'high 'low 'length
'ascending Function attributes for a type
'pos(value) 'val(value) 'succ(value) 'pred(value)
'leftof(value) rightof(value) Function
attributes for signals'event 'active
'last_event 'last_value 'last_active
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Lab
Board setup and test skills LED 8 bit
counter VGA Round ball Audio Multiplexer using
DIP
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Questions?

• Good Luck!