CMOS Transistor Scaling How Much Longer

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CMOS Transistor Scaling--How Much Longer?

• Chenming Hu
• University of California, Berkeley

DAC, June 6, 2000
University of California, Berkeley
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Acknowledgement

• Research sponsored by DARPA, (Dr. Dan Radack,
  Program Manager)
• Xuejue Huang, Wen-Chin Lee, Charles Kuo,Digh
  Hisamoto, Leland Chang, Jakub Kedzierski,Erik
  Anderson, Hideki Takeuchi, Yang-Kyu Choi,Kazuya
  Asano, Vivek Subramanian, Tsu-Jae King, Jeffrey
  Bokor

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MOSFET Scaling Limits

• Gate Oxide Thickness
• Junction Depth
• Dopant Density Fluctuation

P. Packan (Intel), Science, 1999
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Smaller FET Needs Thinner Gate Oxide

• The conduction channel must be controlled by the
  gate, not by the drain. As L is reduced,
  drain-to-channel capacitance increases.
• Therefore, gate-to-channel capacitance must also
  be raised, i.e., oxide must be thinner.
• 1975 100nm, 2000 2nm. How much thinner can it
  get?

L
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12Å Gate Oxide is Manufacturable-- 4 SiO2
Molecules Thick
G. Timp (Lucent) IEDM, 1999
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SiO2 is Too Leaky Below 1.2nm
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Worse Yet
Even very thin oxide cannot block leakagecurrent
paths that are far from the gate.
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International Technology Roadmap for
Semiconductors (1998 and 1999)
Year
2017
2020
2002
2005
2008
2011
2014
2023
2026
130
100
70
50
35
25
18
13
10
Technology
nm
nm
nm
nm
nm
nm
nm
nm
nm
Gate Oxide
0.8-1.2
0.6-0.8
1.5-1.9
1.0-1.5
0.5-0.6
Ion
Solution Being Pursued
No Known Solution
End of the Roadmap
Chenming Hu UC, Berkeley
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Two Solutions
Double Gate
Ultra-Thin Body
Gate
Gate
Source
Drain
Drain
Source
Oxide
Gate
Common feature A thin body such that no
conduction path is far from the gate.
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Thick Source Drain Needed toReduce Parasitic
Resistance
Double Gate
Ultra-Thin Body
Gate
Gate
Source
Drain
Source
Drain
Oxide
Gate
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Ultra-thin-body FET Electron Microscope Picture
of Gate and Oxide
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Ultra-thin-body FET Demonstration
Effective L40nm and Tsi 20nm
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Simulation of 18nm Ultra-Thin-Body MOSFET
Lg
D
S
G
TSi
BOX
Tox1.5nm / Vds1.0V Nsub1e15cm-3
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FinFET
Body is a thin silicon Fin
Double-gate structure raised source/drain
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Electron Microscope Picture
after Source/Drain etching
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Electron Microscope Picture
after Spacer Formation
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Electron Microscope Picture
after Gate Formation
P poly Si0.4Ge0.6
SiGe gate
Nitride spacer
BOX
Gate
Source
Drain
SiO2 Hard mask
BOX

• Sacraficial oxidation (15 nm)
• Gate oxidation (2.5 nm)
• SiGe deposition (200 nm)
• I-line lithography and Etch

Source
Drain
100 nm
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FinFET with 45nm Gate

• Highest reported PMOS drive current!
• S 69 mV/dec
• If Vt is raised by 0.1 V, Ioff would be 8 nA/um

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FinFET with 18 nm Gate

• Good transistor behavior demonstrated.
• New record of gate length!

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10 nm FinFET Design Simulation
FinFET can be scaled down to 10 nm!
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1935 British Patent Issued to O. Heil
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A Vertical Double-Gate MOSFET
C. Hu (UCB), Proc. 1979 IEEE Power Electronics
Specialists Conference, p.385
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International Technology Roadmap for
Semiconductors (1998 and 1999)
Year
2017
2020
2002
2005
2008
2011
2014
2023
2026
130
100
70
50
35
25
18
13
10
Technology
nm
nm
nm
nm
nm
nm
nm
nm
nm
Gate Oxide
0.8-1.2
0.6-0.8
1.5-1.9
1.0-1.5
0.5-0.6
Ion
Solution Being Pursued
No Known Solution
End of the Roadmap
Chenming Hu UC, Berkeley
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Miniaturization has led to rapid growth of
semiconductor market
Source VLSI Research Inc. United Nation
yearbook World Bank Database IMF
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If Past Trends Continue in the Future
2000 2025   CMOS Technology Generation 180nm 10n
m   Semiconductors as of GWP 0.7 5.6   World
Semiconductor Sales 160B 8,000B or 3,500B
in Yr. 2000 dollars
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Summary

• New FET design and world-record size
  demonstrated.
• Challenges abound from here to production.Years
  of future development needed.
• New FET designs can allow 20x reduction ingate
  length, the same factor achieved in thepast 25
  years.
• Microelectronics will continue to proliferate at
  a fast pace in the next 25 years and perhaps much
  longer.

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