The LC3 Part I

1
The LC-3 Part I

• Chapter 5

2
Outline

• The ISA Overview
• Memory, Registers, Instruction Set, Opcodes,
  Datatypes, Addressing Modes, Condition Codes
• Operate Instructions
• ADD, AND, NOT
• Data Movement Instructions
• PC-Relative Mode, Indirect Mode, BaseOffset
  Mode, Immediate Mode, Examples

3
ISA

• The ISA specifies all the information about the
  computer that the software needs to be aware of.
• Who uses an ISA?
• What is specified?

4
LC-3 Memory Organization

• Address space
• Addressability
• Word Addressable/Byte Addressable?

5
LC-3 Registers

• General Purpose Registers
• Is the PC considered to be a GPR?
• Conventions

6
LC-3 Instruction Set

• Instruction
• Op Code
• Operands
• Instruction Set
• Op Codes
• Operate
• Data movement
• Control
• Data Types
• Addressing Modes

7
How Many Instructions?

• Lots

• Few

8
Indicates instructions that modify condition
codes
9
Indicates instructions that modify condition
codes
10
Addressing Modes

• Where can operands be found?
• 1
• 2
• 3

11
Addressing Modes

• Immediate or Literal
• Register
• PC-relative
• Indirect
• Base Offset

12
Condition Codes

• N - Negative
• Z - Zero
• P - Positive
• When are condition code registers set?

13
Operate Instructions

• NOT
• Addressing mode?

14
Operate Instructions

• ADD, AND
• Addressing Mode?

15
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
16
Data Movement Instructions

• GPR ? Memory
• GPR ? I/O Devices
• GPR ? Memory ???
• Memory ? GPR ???

17
Data Movement Instructions
18
Basic Format
These encode information on how to form a 16 bit
address
19
Data Movement Instructions

• PC-Relative Addressing

20
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
21
Data Movement Instructions

• Indirect Mode

22
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
23
Data Movement Instructions

• Base Offset

24
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
25
Data Movement Instructions

• Immediate Mode

No memory access!
26
Example
GPR's
x0000
x1000
x2000
x3000
x4000
x5000
x3000 0010 010 000000111 x3008 0000 0000 0000
0001
x6000
x7000
27
Example
GPR's
x0000
x1000
x2000
x3000
x4000
x5000
x3000 1010 011 000000111 x3008 0011 0000 0001
0000 x3010 0000 0000 0010 1010
x6000
x7000
28
Example
GPR's
x0000
x1000
x2000
x3010
x4000
x5000
x3000 0111 110 011 000011 x3010 0000 0000
0010 1010 x3011 0000 0000 0000 0000 x3012 0000
0000 0000 1111 x3013 0000 0000 1111 0000
x6000
x7000
29
Example
GPR's
x0000
x1000
x2000
x0000
x4000
x5000
x3000 1110 011 0 0000 1111 x3010 0000 0000
0010 1010 x3011 0000 0000 0000 0000 x3012 0000
0000 0000 1111 x3013 0000 0000 1111 0000
x6000
x7000
30
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