Title: IEEE 802.15 <subject>
1Project IEEE P802.15 Working Group for Wireless
Personal Area Networks (WPANs) Submission Title
STMicroelectronics proposal for IEEE 802.15.3a
Alt PHY Date Submitted 07 March,
2003 Source Philippe Rouzet (Primary) Didier
Helal (Secondary) Company STMicroelectronics Ad
dress STMicroelectronics, 39 Chemin du Champ des
Filles 1228 Geneve Plan-les-Ouates,
Switzerland Voice 41 22 929 58 66 or 41 22
929 58 72, Fax 41 22 929 29 70,
E-Mailphilippe rouzet_at_st.com ,
didier.helal_at_st.com Re This is a response to
IEEE P802.15 Alternate PHY Call For Proposals
dated 17 January 2003 under number IEEE
P802.15-02/372r8 Abstract This document
contents the proposal submitted by ST for an IEEE
P802.15 Alternate PHY based on UWB
technique. Purpose Presentation to be made
during March IEEE TG3a session in Dallas,
Texas Notice This document has been prepared to
assist the IEEE P802.15. It is offered as a
basis for discussion and is not binding on the
contributing individual(s) or organization(s).
The material in this document is subject to
change in form and content after further study.
The contributor(s) reserve(s) the right to add,
amend or withdraw material contained
herein. Release The contributor acknowledges and
accepts that this contribution becomes the
property of IEEE and may be made publicly
available by P802.15.
2STMicroelectronics Proposal forIEEE 802.15.3a
Alternate PHY
- March 2003, Dallas, Texas
Philippe Rouzet D. Hélal, R. Cattenoz, C.
Cattaneo, L. Rouault, N. Rinaldi, L. Blazevic, C.
Devaucelle, L. Smaïni, S. Chaillou, M. Frigerio
3Contents
- UWB PHY Proposal
- Modulation and Principle
- System Block Diagram
- Assets
- Performances at 110Mb/s
- PHY protocol Criteria
- MAC protocol Enhancement Criteria
- General Solution Criteria
4Proposed Modulation
- Pulse Position Polarity
- Modulation
- 1 to Np positions 1 / -1
- Number of bits per pulse 1log2(Np)
Positive Polarity
Negative Polarity
Position 2
Position 1
Position Np
5Flexible Modulation for data rate scalability
CODE RATE Modulation PRP (ns) PAYLOAD Bit Rate (Mbps)
1/3 2PPM pol 6.05 110
2/3 2PPM pol 12.1 110
1/2 4PPM pol 13.6 110
1/2 2PPM pol 5 200
2/3 2PPM pol 6.65 200
1/3 4PPM pol 5 200
2/3 4PPM pol 10 200
7/8 4PPM pol 5.45 480
Adaptive Pulse Repetition Period (PRP)
6 FRAME Known Training Sequencefor Frame
Synchronization and Channel Estimation
PRP
Time Hopping Polarity
2-PPM Polarity (Time Hopping optional)
- Example of a simplified emitted pulse train
- Pulse shape not shown (use rectangle for clarity)
7BEACON is a regular frame with appended
preamble for Coarse Synchronization
Beacon Preamble
Piconet Information
Frame Sync. Ch. Est
Coarse Sync.
PRP
Time Hopping Polarity
Time Hopping Polarity
2-PPM Polarity (Time Hopping optional)
8Demodulation is performed by Match-Filtering
Demodulation
Match-filtering
Rx signal
Tx signal
Channel Estimation
Average
Compound Channel Response
Channel Noise
- The match-filter is the estimate of
- the pulse signature through channel propagation
- No pulse shape is assumed by receiver !
- Take advantage of multi-path (complete immunity)
9Proposed Alternate PHY enables Single Chip FULL
CMOS solution
- Through
-
- DIRECT SAMPLING on 1 BIT
-
- DIGITAL MATCHED FILTERING
- Learn pulse signature after channel propagation
10Compliant with existing MAC IEEE 802.15.3
- Introduction of minor adaptations to optimize
receiver power consumption and complexity - MCTAs and Slotted Aloha used instead of CAP (CCA
difficult with UWB-PHY) - Approximate frames Times Of Arrival (TOAs)
- Announced by source DEV at the begining of CTA
- Used for channel estimation synchronization
11UWB System-on-Chip Block Diagram
TX Data
TX Preparation
Frag-mentation
Channel Coding
Modulation coding
TX Control
PTC
Channel estimation Synchronization
RX Control
Demodulation
Channel Decoding
RX Data
Defrag- mentation
Baseband block
MAC block (Bottom part)
ABR Adaptive Band Rejection
PTC Piconet Time Control
MACBBRF on same silicon except BP filter and
Antenna
12Proposal forIEEE 802.15.3a Alternate PHY
Performances at 110Mb/s
13Typical Pulse Shape
BW-10dB 7GHz
14Link Budget at 110Mb/s at 10m
Noise figure for all RX chain referred at the
antenna output
Optional
Antenna
Pulse Generator
TDD
Switch
Clock Synthesizer
2dB loss
1dB loss
G 16dB
1-bit ADC
LNA
NF 3.5dB
2dB
NF 9dB
Implementation loss 3dB due to jitter (lt10ps
rms) 2dB margin use simplest demodulation
15System Performances
20Gsamples/s 1-bit ADC
MODE CODERATE Modulation PRP (ns) PAYLOAD Bit Rate (Mbps) PAYLOAD Bit RateTarget (Mbps) Eb/No
0 1/3 2PPM pol 6 111 110 6.75dB
1 2/3 2PPM pol 12 111 110 6.6dB
PER
PER
Eb/No
Eb/No
CM3 Channels, Turbo Code (2/3) PRP 12ns, 2PPM
pol
CM4 Channels, Turbo Code (1/3) PRP 6ns, 2PPM
pol
16PHY-SAP Data Throughput close toPayload Bit Rate
Payload Bit Rate (Mb/s) PHY-SAP Throughput (Mb/s) 5 frames PHY-SAP Throughput (Mb/s) 1 frame T_DATA (1020 Bytes MPDU)
110 (mandatory) 101.63 97.73 74.18 ?s
200 (optional) 174.44 163.27 40.8 ?s
480 (optional) 356.57 312.82 17 ?s
Optimized Packet Overhead Times
T_PA_ INITIAL T_PHYHDR T_MACHDR T_HCS T_MIFS T_SIFS T_PA_ CONT T_RIFS
3?s 0.145 ?s 0.727 ?s 0.145 ?s 1?s 5?s 3?s 10 ?s
PHY Header, MAC Header (802.15.3 format), HCS use
110Mb/s mode
17Signal Acquisition in superframeStep 1 Coarse
synchronization during Beacon Preamble.
-
- Acquisition sequence Quadratic-Congruence
Hadamard - Very good cross-correlation and spectral
properties - Minimizes ISI effect
- 03/030 imposes max. duration 20 ?s PRP
10ns - -gt max. length L 2000 pulses
- False Alarm Probability 10-4
- Miss Detection Probability 10 4
Acquisition
Cm3 Single Piconet
Free Space AWGN 10m Acq. time 480 ns (L48)
Multipath Channel 10m Acq. time 900 ns (L90)
18Step 2 Frame synchronization only during Frame
Preamble
- Joint Channel Estimation and Frame
Synchronization - Estimation valid during channel stationarity
(1ms) - Quadratic-Congruence Hadamard sequences 3 ?s
- Use of approximate frame TOAs to manage different
lengths of frames
MIFS
MIFS
MIFS
MIFS
MIFS
Frame 4
Frame 5
MIFS
3
6
MIFS
Frame 1
Frame 2
CTA slot in superframe
TOA 1
TOA 2
TOA 3
TOA 4
TOA 5
TOA 6
CTA Header announcing TOAs
19Simultaneously operating Piconets
- UWB interferers transmit continuously
- RX Power RX sensitivity 6dB
Hypothesis
1- Frame synchronization / Channel estimation
/Demodulation Multipath Channel 10m dmin 1.7
m
Multiple Piconets
Free Space AWGN 10m dmin 0.75m (L2000)
Multipath Channel 10m dmin 2m (L2000)
2- Coarse synchronization
20Adaptive channel coding
- Turbo codes PCCC (Parallel Concatenation of
Convolutional Codes) - Code rate 1/3. With puncturing1/2, 2/3,7/8.
- RSC (recursive systematic convolutional)
13,15(octal def.). - Block size 512.
- Low latency 5 ?s
- Optional Convolutional codes for lower complexity
- Code rate 1/2. With puncturing2/3,7/8
- Constraint length 7 -gt 133,171
21Interference and Susceptibility
- System supports low Signal-to-Interferer-Ratios
- SIR gt -50dB for any in-band narrow-band
Interferer - Adaptive Band Rejection
- 802.11a OFDM interferer SIRgt-30dB (at 5.3GHz
or other) - Generic in-band interferer SIRgt-30dB (at any
frequency) - BaseBand Filtering rejection SIR gt -20dB
-
- All out-of-band interferers supported (according
to IEEE 802.15-3a proposed criteria).
22Low Power Consumption
- Baseband MODEM down to 220 kGates in 2PPM at f
1/PRP - 60 gates (channel estimation) in stand-by during
gt90 of frame time - Plus CODEC (60k to 500 kGates depending on
architecture) - RF Power consumption RXlt 70mW - TX lt 40mW
- 20Gsample 1-bit ADC consumes less than 30mW
- Full Scalability
- Data throughput is adjustable (flexible
modulation) - Compatibility between High and Low Data Rate
devices - Simultaneously operating piconets supported
- Complexity decreases along with data rate
- Power consumption decreases with data rate
23Coexistence and regulatory impact
- Coexistence with in-band systems ensured by TX
pulse shaping or filtering - System is independent from pulse shape
- Transmit power control reduces interferences
- Helped by location awareness capability (distance
can be estimated with 3cm resolution) - No impact on current regulation
- FCCs Part 15 rules followed
- Additional spectrum protection
- can be supported
- 802.15.3 Power Management modes are supported
- (DSPS, PSPS, APS)
24Easy Manufacturability and attractive form factor
- Full system can be built in CMOS technology
- single chip
- Die size estimated at less than 5mm2 in 0.13?m
- Antenna size expected 3cm x 3cm
- Time to Market can be less than 1.5 years !
-
-
25System Margins
10m 4m 1m
110Mb/s 4dB 12dB 24dB
200Mb/s 1.4dB 9.4dB 21.4dB
480Mb/s - 5.6dB 17.6dB
1Gb/s - 2.4dB 14.4dB
NO NEED TO INCREASE ADCs SAMPLING RATE RF
FRONT-END REMAINS THE SAME AT ANY DATA-RATE HIGH
and LOW data rate devices consume SAME POWER at
SAME DATA-RATE
26CRITERIA REF LEVEL STM RESPONSE
General Solution Criteria General Solution Criteria General Solution Criteria General Solution Criteria
Unit Manufacturing Complexity 3.1 B Low - Single chip solution
Signal Robustness Signal Robustness Signal Robustness Signal Robustness
Interference and Susceptibility 3.2.2 A Out-band and In-band Interferers rejected at down to 0.3m
Coexistence 3.2.3 A Pulse shaping or filtering
Technical Feasibility
Manufacturability 3.3.1 A Easy - full CMOS
Time To Market 3.3.2 A 1.5 year
Regulatory Impact 3.3.3 A Flexible emitted pulse shape
Scalability 3.4 C Scalable data rates, ranges and power consumption
Location awareness 3.5 C Supported built in hooks
MAC Protocol Enhancement Criteria MAC Protocol Enhancement Criteria MAC Protocol Enhancement Criteria MAC Protocol Enhancement Criteria
MAC Enhancements And Modifications 4.1 C Compliant
27CRITERIA REF. LEVEL STM RESPONSE
PHY Protocol Criteria PHY Protocol Criteria PHY Protocol Criteria PHY Protocol Criteria
Size And Form Factor 5.1 B Single Chip 5mm2
PHY-SAP Payload Bit Rate Data Throughput PHY-SAP Payload Bit Rate Data Throughput PHY-SAP Payload Bit Rate Data Throughput PHY-SAP Payload Bit Rate Data Throughput
Payload Bit Rate 5.2.1 A All rates supported up to 1Gbps (Low Data Rates)
PHY-SAP Data Throughput 5.2.2 A Short preamble and inter-frame space
Simultaneously Operating Piconets 5.3 A Different preambles for piconets THpolarity code division
Signal Acquisition 5.4 A Short synchronization time (good sequence/continuous sampling)
Link Budget 5.5 A Margin is 4dB at 10m (2dB for lowest complexity)
Sensitivity 5.6 A -73dBm (-75dBm for lowest complexity)
Multi-Path Immunity 5.7 A Channel Estimation Matched-Filter Retrieves all energy
Power Management Modes 5.8 B All modes supported
Power Consumption 5.9 A Very Low. ADC already scaled for highest data-rates
Antenna Practically 5.10 B 3cmx3cm printed
28Proposal matches all criteria at Very Low Cost
and Very Low Power Consumption
Thank you for your attention Questions are
welcome
29BACKUP SLIDES
30Channel Estimation Algorithm
- The channel response is estimated with the
training sequence - Coherent integrations (on the received pulses)
reduces noise and ISI effects. - Most of channel energy is recovered by so.
-
- SNR at RX is good enough to reduce PRP and to
increase data rate. - System is independent from transmitted pulse
shape - No need for Pulse Template
31channel decoding architecture
Uncorrelates bit errors at the input of the
decoder Ccode rate BTCTurbo code block length.
demapping and soft A priori per bit Probability
calculations.
Adds scalability
Channel estimation
depuncture
channel decoder (Turbo decoder or Viterbi decoder)
NPPM Correlations
Deinterleaving BLBTC/C
descrambling
APP calculations
RF
N-PPM (number of Pulse positions) soft values
corresponding to each PPM position at Pulse
Repetition Frequency.
32Turbo code
- Latency is mainly due to the storage of one block
into the channel de-interleaver. - _at_110Mbps 512/110e65us.
- _at_ 55Mbps 512/55e610us.
- Complexity
- RAM 50 000 bits.
- 500 kGates (Current estimation).
33Scenario
MAC considerations
Cell synch
Cell synch
Frame synch
Superframe N
Superframe N1
Contention Free Period
Beacon
Contention Access Period
MCTA 1
preamble
CTA m
header
body
MCTA n
CTA 2
CTA x
CTA 1
preamble
34Preamble Training Sequence Design
- Quadratic-Congruence Hadamard sequences
- TH positions
- Polarity derived from row of a Hadamard matrix
of size (L 1) x (L 1) - Used both for beacon training sequences and for
frame training sequences
- L length of sequence
- i 1,2,,L-1 sequence number
- n 0,1,,L-1 TH offset index
- Good spectral properties
- e.g. 11 dB smoother spectrum
- Compared to any TH code with L 79
Good peak to side-lobe ratio L/2 e.g. 16 dB with
L 79
80
70
0
60
-5
-10
50
-15
40
-20
dB
30
-25
-30
20
-35
10
-40
0
-45
-50
-10
-0.5
0
0.5
0
1000
2000
3000
4000
5000
6000
7000
fT
p
Autocorrelation function for L79
Spectrum with TH polarity, L79
35Coarse synchronization
- Performance Indicators
- False Alarm probability (PFA) a preamble is
detected where there is none - A target PFA 10-4 is assumed
- Missed Detection probability (PMD) the preamble
is not detected - A target PMD 10-4 is assumed
- Beacon training sequence length
- overhead percentage
- synchronization time
- Hypotheses
- No clock jitter present
- No clock drift present
- Send at max power allowed by FCC
- Maximum beacon training sequence length 20 ?s
- Superframe 10 ms
- 4 scenari studied
- CM3 channels utilised
36PMD vs. SNR, for different beacon training
sequence lengths, no jitter, CM3 PFA 10-4
(constant) PRP 10 ns
0
10
-1
10
-2
10
Max expected loss due to jitter 1-2dB
D
M
P
-3
10
-23.3
-17.2
-10.9
-3.1
-4
10
-13.9
-7.2
-20.3
-5
10
-25
-20
-15
-10
-5
0
SNR dB
37Coarse synch Scenario 1
Detectability
D1 Ps -Pn NF Gjitter Gduty-cycle -73 75
7-2 20 13 dB
- For meeting target performances
- sequence length needed L 48
- PRP 10 ns gt sequence duration 4810ns 480
ns - Pulse width 100ps
38Coarse synch Scenario 2
Detectability
D2 -10log10(3) - 20log10(10/d) NF Gjitter
Gduty-cycle -13.77 dB 20log10(d)
- Use largest beacon training sequence allowed 20
?s - PRP 10 ns gt L 2000
- Dtarget -10.3 dB
? dmin 1.50 m
39Coarse synch Scenario 3
Detectability
D3 D1 Gchannel Gmultipath 13 8.5 4.5 dB
- For meeting target performances beacon training
sequence length needed L 90 - PRP 10 ns gt sequence duration 9010ns 900
ns
40Coarse synch Scenario 4
piconet 2
Detectability
D4 D2 Gmultipath -22.27 dB 20log10(d)
- Use largest beacon training sequence allowed 20
?s - PRP 10 ns gt L 2000
- Dtarget -10.3 dB
? dmin 4 m
41Channel estimation Simulation Results
- Loss due to reduction of training sequence length
from 6?s to 3?s equals 1dB
42Clock synchronization
- Goal align DEVs clock frequency to PNCs (drift
correction) - Continuously performed over subsequent superframe
beacon preambles - Filter correction feedback
1
0.8
0.6
0.4
0.2
Normalized Amplitude
0
76 ps
-0.2
-0.4
-0.6
-0.8
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
Time ns
Pulse autocorrelation function
43Timeline
- Coarse synchronization
- Assumed number of different beacon training
sequences for PNCs 8 - DEVs search in a serial manner one among the 8
sequences - At each superframe, one new sequence is searched
for - Superframe length 10 ms ? worst search time
80 ms - Clock synchronization
- Is performed continuously, based on beacon
training sequences - Frame synchronization
- Performed on frame training sequence
- If failed, frame is lost
44Pulse Repetition Period at 110Mb/s
CR Code Rate All PRP values in nanosecond
Low order modulation preferred to minimize gate
count/cost for low data-rate devices
45Pulse Repetition Period at 200Mb/s
CR Code Rate All PRP values in nanosecond
Low order modulation preferred to
enable intermediate data-rate devices
46Pulse Repetition Period at 480Mb/s
CR Code Rate All PRP values in nanosecond
Larger PRP preferred to avoid too small
inter-position delay !
47Pulse Repetition Period at 1Gb/s
CR Code Rate All PRP values in nanosecond
Larger PRP preferred to avoid too small
inter-position delay in PPM
48Manufacturability
- Architecture matches full CMOS implementation
- Low cost, single chip product
- Using todays silicon technology
- Simulation proven hardware architecture
- SystemC model used
- Performance and gate complexity estimated
- Demonstrator in development
- 0.13 ?m CMOS technology
- Size and form factor
- Single chip silicon allows small size like PC
card, memory stick, , and would be usable in
portable devices
49Estimated Gate Count (DEMOD)
50Power consumption
- Low power Architecture
- Minimum RF front end (low power with respect to
alternative architecture) - Demodulation processed in digital
- Channel estimation gates (2/3 of demodulation
count) used only during frame preamble (lt10 of
time) - Typical clock frequency is PRP (only RF front end
is high speed) - Digital power consumption will scale as Moores
law in future technology
51Scalability
- Low data rate (LDR) permits lower power, lower
complexity - Channel estimation power cost can be reduced for
low data rate (need less path, and shorter
sequence) - Simple modulation (polarity) compatible with HDR
devices - High data rate scalable easily
- ST expect data rate of up to 750 Mbps shortly
- 1 Gbps theoretically possible
52Location awareness
- Relative location (distance between stations)
available at almost no cost - Thanks to channel estimation principle
- 2 performance levels possible (implementor
choice) - A few decimeters accuracy (simple processing)
- A few centimeters accuracy (signal processing of
estimated channel) - Minimal additional hooks in 802.15.3 MAC
53Multipath immunity
- Channel estimation principle allows capture of
most received energy - Equivalent to infinite rake architecture
- Excellent performance in worst multipath
environment - Pulse shape/spectrum independent
- The receiver architecture dont need a-priori
knowledge on pulse shape (this is why it is so
easy to match specific regulation) - Dense multipath channel with overlapping pulses
dont degrade performance