Analysis and Design of LowEnergy FlipFlops Dejan Markovic, Prof' Robert Brodersen, Prof' Borivoje Ni

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Analysis and Design of Low-Energy
Flip-Flops Dejan Markovic, Prof.
Robert Brodersen, Prof. Borivoje Nikolic

• Energy per transition (0-0, 0-1, 1-0, 1-1)
• Clocked nodes
• Internal (non-clocked) nodes
• External load

• In low-energy, constant throughput systems,
  supply voltage is often scaled down to minimize
  energy consumption
• Energy consumption of the clocking sub-system is
  about 30 - 60 of the total system energy
• Clock Distribution Network
• Buffers
• Wires
• Clocked Storage Elements
• The design of the clocking subsystem has to be
  resistant to noise and timing failures for robust
  circuit operation
• Variety of flip-flop design techniques
• Conventional master-slave latch-pairs and
  pulse-triggered latches
• Other techniques, often derived from the
  conventional techniques, use double-edge-triggerin
  g, reduced-swing clock, or internal clock gating

• Basic metrics
• tCLK-Q
• Setup
• Hold
• System-level
• D tCLK-Q Setup
• R tCLK-Q - Hold

EAVG ?0-0E00 ?0-1E01 ?1-0E10
?1-1E11

• E ?CswVswingVDD
• Reduce each term in the product expression
• delay is overlooked
• Circuit sizing that yields an optimal EDP
• Minimize clocked capacitances to compensate for
  increased switching activity
• Size circuits to optimally drive output load
  equivalent to 4 standard loads
• Sizing methodology based on Logical Effort
• Quantifies driving capability of a logic gate
  relative to a standard inverter
• Correlation can be established between transistor
  sizes and computed logical effort
• Difficult to size flip-flops to minimize EDP
  directly ? derive limit cases of minimizing delay
  for given energy
• Limit to minimization of transistor sizes is set
  by the substrate noise immunity
• Key to minimizing circuit speed is active circuit
  that is responsible for flip-flops performance

• Pulse-Triggered are fastest but exhibit small
  internal race immunity
• TGFF suitable for large-scale designs with high
  clock skew
• Gating introduces big penalty in delay

a) Clock-on-Demand FF COD-FF (Kuroda, ISSCC00)
b) Transmission-Gate FF with Internal
Gating GTGFF

• Flip-flop characterization metrics that offer
  novel insights into flip-flop behavior at both
  the circuit and system levels are presented
• Systematic approach to the transistor sizing
  issue completes the basic principles in
  low-energy flip-flop design for voltage-scaled
  digital systems
• Internal clock gating is effective for low input
  switching probabilities, when added to the TGFF
• TGFF is the best choice for low-energy digital
  design
• good energy-delay trade-off
• good race margin
• good noise robustness
• small energy required to drive its data and clock
  inputs

The key trade-off in energy saving capabilities
of FFs w/ internal clock gating is the balance
between the energy overhead in the internal
clock gating and energy savings in clocked
nodes Internal clock gating is effective when
the clocked transistors are large and/or when
data activity rates are low

• D and R show very little variation with clock
  slope
• Clock skew specification is a linear function
  of the mismatch in
• clock slopes of two back-to-back connected
  flip-flops

Increase in size of clocked transistors changes
energy saving capability of FFs with internal
clock gating