On-Chip ECC for Low-Power SRAM Design

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On-Chip ECC for Low-Power SRAM Design

• Hsin-I Liu
• EE 241 Project
• 5/9/2005

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Outline

• Introduction to low-power SRAM
• Introduction on error correction code
• Analysis of data retention voltage in SRAM
• Simulations and results

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Low-Power SRAM

• Concept Reduce the standby Vdd to data retention
  voltage (DRV)

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Modeling DRV
DRV is modeled as i.i.d. gamma random variable
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Error Correction Code

• Adding parity check into information
• Non-trivial binary code
• Easy to encode
• Parameters fixed
• Hamming code, Golay code
• Linear block code
• Parameters flexible
• Reed-Solomon code
• Least parity overhead

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Applying ECC to SRAM

• Latency
• In proportional to block size
• In this project Hamming (15,11), Golay(23,12),
  and RS(15,11)
• Implementation characteristics are well-known

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Model Setup
Memory size M N
ECC block size n info length i
Row redundancy r rows
Standby cycles T
Metrics
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Model Analysis

• For certain standby voltage, retention ability
  can be modeled as Bernoulli r.v.
• For certain pe of a row, pe of a block can be
  derived
• Inside a block, pe of each cell can be found by
  solving binomial distribution
• Row redundancy can also be modeled as binomial
  r.v.

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Results
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Results (cont.)
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Results (cont.)
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Conclusion

• Hamming code introduces the least overhead
• For short waiting time, Hamming code can reduce
  Eb from 50 to 2x
• As waiting time goes to infinity, Reed-Solomon
  saves the power by 3x