SLINK

1
SLINK

• Current Progress

2
Hardware Setup
Control via VXI-MXI-2
FED Controller
VME Backplane
FED
LVDS Cable
Slink Controller
3
Slink Verification
FED PC
SLINK PC

• Configure FED to send test patterns
• Simple counter
• Alternate lines of all As and all 5s
• Drive FED with software triggers
• Throttle triggers using software waits and by
  setting QDR buffer occupancy thresholds

• Simply receives all data sent from FED
• Compares received data with current expected test
  pattern

4
Example Data Transmission
Test Pattern Alternate lines of As and 5s,
Scope Length 10 Measured from Transition Card
5
A Bad Clock?
Test Pattern Alternate lines of As and 5s,
Scope Length 10 Measured from Transition Card,
Persistent Display
6
Clock Signal at the FED
Measured on the FED Slink Connected
7
Clock Signal at the FED
Measured on the FED Transition Card Disconnected
Green Slink CLK Yellow Write Enable Blue Bit
0 of Data Stream Pink Bit 1 of Data Stream
8
Spice Model of Clock Path
9
Spice Model Results
Blue CLK at FED VME connector Red CLK at output
connector on Transition Card Yellow CLK at input
to Transmitter FPGA
10
The Only Way to Remove Reflections?
11
The Only Way to Remove Reflections?
CLK is good at all locations but impractical
hardware solution
12
Clock at Input to Transmitter FPGA
The Slink clock is clean where it matters, as
Spice model predicts
13
Slink Error Rates

• Have sent 18.3 Gbytes of data from FED to Slink
  Receiver
• Used alternate lines of all As and all 5s
  highest possible switching rate
• No errors observed in transmitted data
• ? Probability that a word will be transmitted
  incorrectly via Slink is

1.22 x 10-9 _at_ 95 CL
14
Required Data Rates

• To guarantee (95 CL) that no more than 1 word
  will be sent incorrectly per month of normal LHC
  operation, need to transmit words
  (without errors)
• At current maximum data rate, would take 16
  years!
• Need to find a way to increase data rate
• Could potentially output 600 Mbytes/sec from the
  FED (reducing validation time to 30 days)

15
FED Behaviour at High Data Rates
An Extreme Example Test Pattern Alternate
lines of all As and all 5s, Scope Length 1020

• With a fixed wait of gt 60.07ms between software
  triggers
• QDR buffer always empty when next trigger arrives
• FED operates normally
• With a fixed wait of lt 60.07ms between software
  triggers
• QDR buffer rapidly fills to current limit (1? 10
  frames)
• FED operates normally for some period of time
• FED randomly stops sending data

16
Why Does the FED Stop?

• Backpressure from the Slink?
• At high trigger rates, backpressure is exerted
  multiple times during period in which FED is
  working
• Overflow of QDR Buffer?
• FED stops working even with a QDR buffer limit of
  1 frame
• Overflow of Front End Buffer?
• Backend Status Register would indicate not
• But getChannelBufferOccupancy() function in
  Fed9U software returns dubious values
• Seems most likely cause

x
x
?
17
Data Rate Challenges

• Need to prevent FED lock-ups
• Software triggers insufficient
• Limited to a maximum of 100 Hz
• Need to use hardware triggers - generated with
  FED Tester?
• Need to increase efficiency with which Slink PC
  manages received data
• Currently have to run Slink software in debug
  mode (raw data access) due to mismatch between
  output FED header/trailer words and format
  required for automatic event handling

18
Conclusion

• Data can be read from the FED via Slink
• No errors yet observed
• Nothing to suggest that FED hardware requires
  modification
• Firmware/Data Rate issues to be resolved