EMU SLICE DAQ

1
EMU SLICE DAQ

• Hardware
• Production CFEB, DAQMB, DDU
• Pre-production DCC (slight PCB layout differences
  from production DCC, which is due next month)
• Data Readout
• DDU Gigabit Ethernet Spy-path (waiting for CMS
  DAQ for DCC Slink readout)

2
EMU SLICE DAQ

• Status
• Working Fine, Two one-million-event runs were
  taken without error, except big-physics area
  wrap-around partial events
• Eight chambers are in, but the trigger rate and
  data rate is still far from LHC design, although
  all five CFEBs will trigger if any one is
  triggered.
• The DDU monitoring program will read the DDU
  status through VME, and the program is improving.
  

3
EMU SLICE DAQ

• System (multiple-crate, multiple-board) time-in
• 1. Single Chamber time-in (UCLA procedure)
• 2. Track finder crate time in, so that the L1A
  timing will not depend on chambers (one way is to
  delay the LCTs for CSCs with shorter skew-clear
  cables)
• 3. Adjust the L1A delay, so the latency delay
  between L1A and LCT with longest skew clear cable
  is 3.3us (this number will be changed for LHC)
• 4. Add LCT delay (cable_delay) on DMB (to be
  moved to TMB) for CSCs with shorter skew-clear
  cables, so that all the LCT to L1A latencies seen
  on DMBs are 3.3us.
• 5. Adjust the DAV delays, so that CFEBs, ALCT and
  TMB data will be readout

4
EMU SLICE DAQ

• Problems happened last week (Frank,, re-order
  them as you think suitable)
• 1. ALCT L1A_number counts from 0 by default,
  fixed by set offset 1
• 2. CFEB L1A_number sometimes does not match with
  DMB L1A_number. This is caused by design
  feature, unavoidable. Ignore if not happen in
  concecutive events
• 3. One DMB can not load the new firmware. One DMB
  can not power-on the Low_voltage. Replaced DMBs,
  and need further investigation on the DMBs
• 4. One Skew-clear cable (to DMB) has a bent-pin,
  fixed but the pin is shorter than normal (Replace
  cable?)
• 5. ME2/2/30 Low voltage power supply (7.5V
  digital) is not stable. Cycle the source power
  and fixed, but happened twice
• 6. The DMB guarantee no LV power interruption on
  on-chamber electronics, but does not guarantee
  on-chamber LV power on power_on