Gang Quan - PowerPoint PPT Presentation

About This Presentation
Title:

Gang Quan

Description:

Determines area, cycle time. A Mapping Example. Subject to: Two adders. Four registers ... Scheduling ASAP, ALAP, List-based scheduling. Control/Data Flow Graph ... – PowerPoint PPT presentation

Number of Views:46
Avg rating:3.0/5.0
Slides: 36
Provided by: webCe
Learn more at: http://web.cecs.pdx.edu
Category:
Tags: area | code | gang | list | quan

less

Transcript and Presenter's Notes

Title: Gang Quan


1
Introduction to Data Flow Graphs and their
Scheduling
Sources Gang Quan
2
Computational Models
  • What
  • A conceptual notion for expressing the function
    of a system
  • DFG (Design Flow Graph)
  • FSM,
  • Petri net,
  • Turing machine,
  • etc.
  • Computational Models Languages
  • Models express the behavior, languages capture
    models
  • Models are conceptual, languages are concrete
  • What is in a computational model
  • A set of objects
  • Rules
  • Semantics

Should be big (powerful) enough enough to
precisely express the function of the system with
unambiguity, should be small enough to have
synthesis and verification tools to support it.
3
Data Flow Graph (DFG)
  • A modem communications system
  • Each box is a single function or sub systems
  • The activity of each block in the chain depends
    on the input of the previous block
  • Data driven
  • Each functional block may have to wait until it
    receives a "certain amount" of information before
    it begins processing
  • Some place to output the results

4
Data Flow Graph
  • Definition
  • A directed graph that shows the data dependencies
    between a number of functions
  • G (V,E)
  • Nodes (V) each node having input/output data
    ports
  • Arces (E) connections between the output ports
    and input ports
  • Semantics
  • Fire when input data are ready
  • Consume data from input ports and produce data to
    its output ports
  • There may be many nodes that are ready to fire at
    a given time

5
Data Flow Graph Construction
6
Constant
Multiplication
Square root
Division
Nodes of DFG can be any operators, also very
complex operators
7
Data flow graph construction
  • original code
  • x ? a b
  • y ? a c
  • z ? x d
  • x ? y - d
  • x ? x c

c
d
b
a




-
y
x
z
x
x
8
Data flow graph construction
  • original code
  • x ? a b
  • y ? a c
  • z ? x d
  • x ? y - d
  • x ? x c
  • single-assignment form
  • x1 ? a b
  • y ? a c
  • z ? x1 d
  • x2 ? y - d
  • x3 ? x2 c

9
Data flow graph construction
  • single-assignment form
  • x1 ? a b
  • y ? a c
  • z ? x1 d
  • x2 ? y - d
  • x3 ? x2 c

10
Design Issues for DFGs
  • Allocating operator nodes to resources (blocks,
    functional units)
  • Mapping to blocks
  • Schedule in time
  • Memory management
  • Construction and usage of the queues and other
    special memory resources useful in data flows
  • stacks?

11
What are the goals of these design processes?
  • Guarantee correct behavior
  • Utilize hardware efficiently.
  • Obtain acceptable performance.

12
Allocation
  • Decide the numbers and types of different
    functional units
  • E.g. register allocation

. x lt a b y lt a c x lt x - c . .x
.y.
. x lt a b y lt a c x lt x - c . .x
.y.
three registers
13
Mapping
  • Distributing nodes to different functional units
    on which they will fire
  • Functional units may provide different functions
  • Adder or ALU, MUX or buses, etc
  • Functional units may have different delay
  • Ripple adder or look ahead adder
  • Determines area, cycle time.

14
A Mapping Example
  • Subject to
  • Two adders
  • Four registers
  • b and e cannot be assigned to the same
    register

We assume two adders and four registers and next
do synthesis for this assumption. But how do we
know how many to assume?
15
A Mapping Example
b
a

c
R1
R2
R3
d


Adder 2
Adder 1
f
e
R1 a R2 b, c, e R3 d, f
  • Subject to
  • Two adders
  • Three registers
  • a and e cannot be assigned to the same register

Mapping may not be unique !
16
Scheduling of DFG
  • Schedule
  • Creating the sequence in which nodes fire
  • Determines number of clock cycles required
  • Two simple schedules
  • As-soon-as-possible (ASAP) schedule puts every
    operation as early in time as possible
  • As-late-as-possible (ALAP) schedule puts every
    operation as late in schedule as possible

17
ASAP scheduling for DFG
Start from t0
Nodes fire whenever the input data are available.
18
ALAP Scheduling for DFG

/

-

-1

Nodes fire when absolutely necessary.
Start from the terminal values of t
19
More about ASAP and ALAP
  • Unlimited resources
  • No limit for the number of registers, adders, etc
  • Longest path through data flow determines minimum
    schedule length
  • Mobility
  • tL tS
  • Difference between schedule in ALAP and schedule
    in ASAP.
  • The higher it is the more solutions we can find
    in optimization process

20
Mobility
u here is the mobility list
  • u tL - tS

u
We will use this list in next scheduling
method
0

0
/
ASAP
0
-
1

0

ALAP
2
-1
0

The node mobility represents its flexibility in
the fire sequence.
21
Restrained Scheduling
  • Time constraints
  • Time is given, minimize the resource
  • Resource constraints
  • NP problem

22
Time Constraints
How many units of time the graph needs to
complete (we assume it)
T
6
7
8
2
1
1
/-
2
//
2
1
1
1
1

1
sqrt
1
1
1
-1
1
1
This shows how many various blocks we need if 6
fires.
This shows how many various blocks we need if 8
fires.
23
Resource Constraints
  • Resource is given, minimize the long time
  • List based scheduling
  • Maintain a priority based ready list
  • The priority can be decided by mobility for
    example
  • Fire the nodes according to their priorities
    until all the resource are used in that stage

24
List Based Scheduling
priority based ready list The priority can be
decided by mobility for example Fire the nodes
according to their priorities until all the
resource are used in that stage

/

-
t0

/
t1


-
t2


t3


Such that there is one /-, one //
t4

t5
25
List Based Scheduling
  • A general ASAP
  • Priority based ready list

26
Control/Data Flow Graph (CDFG)
x lt a b if ( x gt 100) y lt a c else
y lt a c endif
27
Control/Data Flow Graph
  • Definition
  • A directed graph that represents the control
    dependencies among the functions
  • branch
  • fall-through
  • G(V,E)
  • Nodes (V)
  • Encapsulated DFG
  • Decision
  • Arces (E)
  • flow of the controls
  • Very similar to FSMD
  • Operation rectangles (instructions) can be vary
    complicated
  • Diamonds for predicates can be very complicated
    and require many clock pulses to complete.

28
CDFG Example
fun0() if (cond1) fun1() else
fun2() fun3() switch(test1) case 1 fun4()
break case 2 fun5() break case 3 fun6()
break fun7()
29
CDFG Example
fun0
N
fun0() while(cond1) fun1() fun2()
cond1
Y
fun2
fun3
30
Design Issues for CDFG
  • Code optimization
  • Loop optimization, dead code detection
  • Register allocation

31
Summary
  • Data Flow Graph (DFG)
  • models data dependencies.
  • Does not require that nodes be fired in a
    particular order.
  • Models operations in the functional modelno
    conditionals.
  • Allocation and Mapping
  • Scheduling ASAP, ALAP, List-based scheduling
  • Control/Data Flow Graph
  • Represents control dependencies

32
To remember
  • Now we know the most important concepts
  • Data Flow Graph (DFG)
  • Control/Data Flow Graph
  • FSM table
  • Transition Graph
  • Combinational Graph (netlist)
  • These concepts alone are sufficient to complete
    all projects in this class.
  • However we will introduce more concepts and
    algorithms so you will be able to find
  • Better solutions
  • In shorter time

33
Homework 3
  1. Find an example of some computation that is
    repeated many times on the same or on different
    data
  2. Draw DFG for this computation
  3. Possibly optimize this DFG using laws of
    arithmetic
  4. Schedule this DFG ASAP. Allocate to resources and
    find cost of hardware and time of processing.
  5. Schedule this DFG ALAP. Allocate to resources and
    find cost of hardware and time of processing.
  6. Schedule this DFG according any other method or
    heuristically using your common sense. Allocate
    to resources and find cost of hardware and time
    of processing.
  7. Make a table comparing all your results you can
    have more than three.
  8. Select one design and give reason for this.
  9. Realize this design as a complete circuit. You
    can use ready adders, multipliers, etc blocks
    from internet.
  10. If you want (option) you may simulate this design
    with Verilog or VHDL or any graphic simulator.
    This is not mandatory part of the homework.

34
Review for Exams (1)
  1. What is in a computational model? Give examples
  2. Why computational models are important? We can
    describe every system as a Mealy Machine? Why
    other?
  3. What is DFG?
  4. Give few applications of DFGs
  5. Give example of a DFG of some hypothetical
    computer that would be worthy to build, for
    instance Hough Transform processor for a robot
  6. What is Allocating?
  7. What is Mapping?
  8. What is Scheduling?
  9. Explain ASAP Scheduling for a practical DFG on
    example.
  10. Do the same example again using ALAP scheduling.
  11. Compare the ASAP and ALAP Scheduling.
  12. What is Constraint Satisfaction Problem (question
    asked again but now you know more)
  13. What is NP, NP complete and NP hard problem. Give
    examples.
  14. Why the concept of NP problems is important?

35
Review for Exams (2)
  1. What is mobility and fire sequence. Give an
    example.
  2. Formulate the scheduling, allocation and similar
    problems as constraints satisfaction problems
    with constraints and costs as energy to be
    minimized.
  3. Give example of List Scheduling
  4. What is CDFG and what are associated synthesis
    and optimization problems?
Write a Comment
User Comments (0)
About PowerShow.com