Nonvolatile Memories and Programmable Logic

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Nonvolatile Memories andProgrammable Logic

• Anselmo Lastra

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TODO

• What PALs do we use
• Look at SOCs

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Topics

• Nonvolatile memory
• ROM
• Reprogrammable ROM (EEPROM, Flash)
• Programmable Logic Devices (PLDs)
• PLA
• PAL
• CPLD
• FPGA

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Read Only Memories (ROM)

• Oldest technology
• Originally mask used as last step in
  manufacturing
• Specify metal layer (connections)
• Used for volume applications
• Long turnaround
• Used for applications such as embedded systems
  and boot ROM

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Programmable ROM (PROM)

• First ones had fusible links
• High voltage would blow out links
• Fast to program
• Had to throw away bad ones

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UV EPROM

• Erasable PROM
• Common technologies used UV light to erase
  complete device
• Took about 10 minutes
• Holds state as charge in very well insulated
  areas of the chip
• Nonvolatile for several (10?) years

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EEPROM

• Electrically Erasable PROM
• Similar technology to UV EPROM
• Erased in blocks by higher voltage
• Programming slow
• Called flash memory
• Digital cameras, BIOS
• Limited life
• One on Xess board has 5 blocks
• Has a boot block that is carefully protected

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Details of ROM

• Memory that is permanent
• k address lines
• 2k items
• n bits

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Schematic of Internals
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Programmed Truth Table
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Resulting Programming
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ROM as Combinational Circuit

• In Ch. 3 saw decoder and OR gates to generate sum
  of products
• ROM implements that logic
• Each output line is sum of minterms of the k
  inputs
• Previous example has 8 functions of 5 inputs

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Example

• A7 is sum of minterms 0, 2, 3, , 35 (octal)
• Implement directly from truth table

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Example 2

• Generate square of 3-bit number

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ROM Implementation

• Short cut for B0 and B1
• Saves space

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Other Types of PLDs
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Programmable Logic Array (PLA)
Like programmable inverter Tied to 0 F1 not
inverted Tied to 1 F1 is inverted
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Programming
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What to Program

• Try to reduce the number of product terms
• To use fewer of the rows
• Number of literals in each term not as important
• Fewer may make circuit faster

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Example

• Functions to implement are

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Minimum Product Terms

• Fewest are

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Table
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Generating Table

• What really gets generated is table (by computer)
• Chip programmed in special-purpose programming
  device
• With personality modules

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PAL

• OR circuit not as versatile
• 4 in, 4 out
• But only 3 ANDs
• Note F1 fed back to minterm
• Possible to expand

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Example
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Simplified

• Can use K-Maps or software
• Example
• Z is larger than 3 terms
• But can reuse W

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Programming Table
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Connections
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Real PALs More Complex

• 1977-late 80s

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The Ones on the Board
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More Complex Devices

• Chips with many PLAs (macrocells)
• Full custom
• Pixel-Planes chips
• Lots of memory
• Standard cell
• Library of cells
• Engineer determined interconnection
• Gate arrays
• Small circuits with interconnect

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Altera CPLD

• Ports to interconnect
• Logic has input and output to interconnect
• Some logic blocks can output from chip

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Macrocell (16 in logic block)

• See http//www.altera.com/literature/ds/m7000a.pdf

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Xilinx FPGA
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Spartan2

• 4K bit RAM blocks
• Large amt of logic
• Program stored in SRAM

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Switch Matrix
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Pass Transistor
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Mux Controlled by Memory
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Logic Lookup Table

• Instead of gates
• So doesnt matter much how you specify your logic
• Ends up truth table

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Xilinx CLB
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Spartan 2

• At right two logic cells (LC)
• Two (four LCs) in CLB
• LUT is small RAM

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CLB

• Muxes can make full 6-input function of sme
  functions w/ up to 19 inputs
• Each LC can be 1 bit of an adder

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Xilinx IOB
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Spartan 2 IOB
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RAM

• Ours has 10 blocks for a total of 40Kbits SRAM

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Device Specs

• See http//direct.xilinx.com/bvdocs/publications/d
  s001_2.pdf

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Others

• Some devices with microprocessor and extra logic
• For control applications
• Can also synthesize controllers
• We have Xilinx software to generate processors

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Today

• Nonvolatile memories
• ROMs
• EEPROMs
• Programmable Devices
• Small PALs PLAs
• Larger PLDs, FPGAs

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Next Time

• Datapaths
• Build up ALUs