A Multicycle Datapath

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• A Multicycle Datapath
• Exceptions

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Basic MIPS

• We want to design a datapath to support a subset
  of the core MIPS instruction set
• Memory reference instructions lw and sw.
• Arithmetical-logical instructions add, sub, or,
  and slt.
• Branch equal (beq) and jump (j).

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Executing Four Instructions

• Describe the sequence of steps performed in the
  datapath in the execution of each of the
  instructions below
• add t1, t2, t3
• lw t1, offset(t2)
• beq t1, t2, offset
• j address (you may have to make modifications
  the datapath to execute a jump)

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Abstract View of Multicycle Datapath
Goal To break up the execution of an instruction
into steps, where each step takes one clock
cycle to complete.
Main differences One memory unit for data and
code, a single ALU, extra registers to hold data
thats passed from one clock cycle to the next.
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Multicycle Datapath Design Principle
One clock cycle must accommodate at most one of
the following operations

• A memory access.
• A register file access (either two reads or one
  write).
• An ALU operation.

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The Need for Temporary Registers

• Instruction Register (IR) and Memory Data
  Register (MDR) save the output of memory
  between different clock cycles. Why two? Because
  both values may be needed during the same clock
  cycle.
• ALU input A and B get data out of the register
  file and hold it until the ALU is ready to
  operate on it.

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The Need for Multiplexors

• Now we have a single ALU which must accommodate
  all the inputs that used to go to the three units
  we used to have.
• The second input to the ALU now needs to have a
  four-way MUX.
• Sometimes the address to the memory will refer
  to data. Sometimes it will refer to instructions.
  This will require another MUX.

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Multicycle Datapath w/Control Lines
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Writing to the PC

• Think about when the program counter (PC) is
  written to
• After an instruction is fetched, it is
  unconditionally incremented by 4 bytes.
• When a jump is executed, it is unconditionally
  written to with the address value.
• What happens in the execution of a branch,
  though?

We need more control signals PCWrite and
PCWriteCond.
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Multicycle Datapath and Control Unit
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Finite State Machine Control
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Instruction Fetch and Decode
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State 0 (instruction fetch) MemRead1,
ALUSrcA0, IorD0, IRWrite1, ALUSrcB01,
ALUOp00, PCWrite1, PCSource00
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State 1 (instruction decode/register fetch)
ALUSrcA0, ALUSrcB11, ALUOp00
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Memory Reference Instructions
State 2 ALUOp is add, sources are one register
and the imm from instruction gt compute c(reg)
reg c.
State 3 read data from memory.
State 4 write data that was taken from
memory into selected register.
State 5 just write the contents of selected
register to memory remember that what
is indexing memory is not the PC!
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R-Type Instructions
State 6 ALU sources will be registers and the Op
comes from the function code.
State 7 write register selection comes from the
instruction and data comes from the ALU output.
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Branch Instructions
In State 1, ALU sources and Op are determined
now I only need to check results and take or not
take the branch.
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Jump Instructions
State 9 establish the that PC source will be the
low 26 bits of the instruction (shifted left
twice) concatenated with the upper 4 bits of
this instruction.
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The Complete Control FSM
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Exceptions and Interrupts

• Definition An exception is unexpected event from
  within the processor (for instance, arithmetic
  overflow).

Definition An interrupt is an event from outside
the processor (I/O devices generate interrupts to
communicate with the processor).
Both exceptions and interrupts cause an
unexpected change in the control flow.
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Exceptions and Interrupts
Something outside the CPU requires
attention control flow also changes unexpectedly.
Unexpected change in control flow.
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Handling Exceptions

• Consider two possible types of exceptions
• Arithmetic overflow
• Undefined instruction

Question How do you think the system should deal
with these events?
Question How does the possibility of having to
handle exceptions change the execution of an
instruction?
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Handling Exceptions
User code is stopped, perhaps temporarily, and a
branch happens to an exception handler. We must
know what caused the interruption so we know
what course of action it demands.
EPC
Cause
register
register
Stores the address of the offending instruction.
Bits in this register indicate what triggered the
exception.
We need control signals to write to these
registers EPCWrite and CauseWrite
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Design Alternatives
Question To which address does the execution
branch when an exception happens?
Alternative 1 Always branch a fixed address
(MIPS) 0xC000 0000. The handler comes up, checks
the cause and takes the appropriate
action. Alternative 2 The address of the branch
is determined by the cause of the exception
(vectored interrupts). For instance, if undefined
instruction happens, branch to 0xC000 0000 if
arithmetic overflow happens, branch to 0xC000
0020.
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Changes to the Datapath
If were always going to branch to 0xC000 0000
when an exception happens, we have to add another
input source to the PC register. Make the MUX
4-way and add another control value to the
selection control gt PCSource 11. We want to
save the address of the offending instruction in
the EPC register, but Complication The PC has
already been incremented by 4. Hook up the data
input of the EPC to the ALU, which is used to
subtract 4 from the current value of the PC.
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Datapath for Exceptions
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The Modified Control FSM