Detector Data Link (DDL)

1
Detector Data Link (DDL)

• DDL hardware
• Csaba SOOS

2
Readout system
Front-end electronics
P2 Cavern
DDL SIU
Detector Data Links
Optical Fibre 200 meters
P2 Access shaft
DDL DIU
RORC
Front- End Digital Crate/Computer
LDC
3
DDL architecture

• Source Interface Unit (SIU) (1)
• Interface to the Front-end Electronics (2)
• Destination Interface Unit (DIU) (3)
• Interface to the Readout Receiver Card (4)
• Full duplex optical link (5)
• Multimode optical cable of up to 200 m

1
3
5
2
4
4
DDL hardware
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DDL interfaces

• SIU-FEE interface
• 3.3V (LVTTL) interface
• 32-bit wide half-duplex data bus (bi-directional
  bus)
• Bi-directional flow control
• User defined clock (synchronous interface)
• JTAG interface
• DIU-RORC interface
• 3.3V (LVTTL) interface
• 32-bit wide full-duplex data bus
• Bi-directional flow control
• User defined clock (synchronous interface)

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SIU-FEE interface

• fbD(31..0) - data lines (bi-directional)
• fbTEN_N - data enable (bi-directional)
• fbCTRL_N - data qualifier (bi-directional)
• fiDIR - bus direction (FEE input)
• fiBEN_N - bus enable (FEE input)
• fiLF_N - link full (FEE input)
• foBSY_N - front-end busy (SIU input)
• foCLK - interface clock (SIU input)
• TAP_TCK - JTAG clock (FEE input)
• TAP_TDI - JTAG data in (FEE input)
• TAP_TDO - JTAG data out (SIU input)
• TAP_TMS - JTAG mode select (FEE input)
• TAP_TRST - JTAG reset (FEE input)

7
DIU-RORC interface

• riD(31..0) - data lines (RORC input)
• riTEN_N - transfer enable (RORC input)
• riSTS_N - data qualifier (RORC input)
• riLF_N - link full (RORC input)
• riLD_N - link down (RORC input)
• roD(31..0) - data lines (DIU input)
• roTEN_N - transfer enable (DIU input)
• roCMD_N - data qualifier (DIU input)
• roBSY_N - RORC busy (DIU input)
• roRST_N - DIU reset (DIU input)
• roCLK - interface clock (DIU input)

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Link management
DIU
SIU
RORC
idle
Power-on
SIU reset
Reset
Power-on
SIU reset
off-line
off-line
Offline
Offline
on-line
on-line
Online
on-line
Online
on-line
Link up
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Front-end control
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Front-end status read
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Event read
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Block write
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Block read
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PCI RORC
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D-RORC
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RORC features

• Interface between the DIU and PCI local bus
• pRORC 32 bit/33 MHz PCI version, max. throughput
  132 MB/s
• D-RORC 64 bit/66 MHz PCI version, max.
  throughput 528 MB/s
• PCI master capability, data push architecture
• Autonomous operation with little software
  assistance
• Supports multi-paged memory management
• Direct data transfer to the PC memory
• No local memory on the board
• Small elasticity buffers between different clock
  domains
• Built-in test capability
• Internal pattern generator can produce formatted
  data

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The Free FIFO
Firmware
page address
Free FIFO
page address
page address
PC CPU
readout
Allocation of free pages
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Direct Memory Access
DDL
Firmware
PC CPU
No involvement
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The Ready FIFO
DDL
Firmware
Ready FIFO
PC CPU
readout
Delivery of filled pages
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Test equipments

• Front-end Emulator Interface Card (FEIC)
• Fully functional hardware to emulate the detector
  front-ends
• Formatted data block generation
• Internal (free running) or external (pulse)
  triggering capabilities
• Adjustable parameters (using front-end control)
• Operates at the nominal speed of the DDL
• Source Interface Unit Simulator (SIMU)
• Simulates the behavior of the DDL without any
  additional hardware
• Eases the development and the hardware debugging
• Size is similar to the real SIU