Midterm 1 Issues

1
Midterm 1 Issues
2
What I am expecting

• Understanding of basic terminology
• Understanding of basic architectural features
• Laboratory skill demonstration
• Syntax
• Design
• Testing and Debugging
• Team programming skill
• Difference to other processors

3
Errors and Defects

• You make a mistake in Midterm 1
• You do a review of your exam and the question
  paper
• If you find the mistake now (before handing in
  the exam) ERROR
• The consequences of that mistake are minimal
• If I find the mistake during marking (the next
  phase of the project) DEFECT
• The consequences of that mistake are major

4
Errors and Defects

• You dont understand something in the lecture
• My phrasing, your background, the ski-trip
  yesterday introduced mistake in understanding
• You immediately ask a question
• Get an answer error in misunderstanding
  corrected
• Time consumed 3 minutes
• You dont ask a question because you did not
  realize that you did not understand the
  something
• You get to the lab, and there are problems
• The laboratory is new to you with many new
  concepts, all of which you thought you understood
• Which of the many concepts is causing the
  problem?
• Defect in misunderstanding
• Much time consumed
• Confidence undermined

5
Errors and defects

• Names are terminology. Need to get the names
  correct so that have common language to use
• Why should I care?
• Need to understand issues when we have to handle
  process improvement at University or on the job
• The ideas behind errors and defects are more
  important than the names
• Certain classes of mistakes are more costly on
  both personal and company level
• Whether found now (in the phase of development)
  or late (out of the phase of development)
• Different terminology same idea
• Humphreys talks about defects in phase and
  defects out of phase (errors in phase,
  mistakes in phase)
• I use the more emotive terms error seems much
  less important than DEFECT

6
Error means mistakes found by compilers

• It is true that mistakes found by compilers are
  errors
• It is NOT true that errors means mistakes found
  by compilers. Errors can be found by other means
  code review, thinking
• The only problem is for many developers, if the
  compiler does not complain, then it must be
  correct
• Unfortunately this means that many developers
  work using a definition a defect is a mistake
  not found by a compiler.

7
I like this definition of an error and its
characteristics mixed from a couple of students
comments

• An error is recognized early as being a
  failure.
• Errors are much easier to fix as they typically
  occur in local functions (functions you are
  developing NOW)
• Defects are recognized later as a failure in
  code (or design) that the developer thought was
  working.
• Defects are hard to fix because they could be a
  failure anywhere.
• Defects are also costlier to fix because the
  problem often has knock-on effects. You may
  have changed some code (which was correct) to
  make an (unrecognized) defect go away.

8
Processor architecture

• Different resources that can be used (as with any
  processor)
• J and K integer alus (I-ALU)
• Cause stalls mainly through memory accesses
• Additional stalls if values get changed and then
  are immediately used (in this instruction or the
  next)
• X and Y compute blocks
• Stalls if values get changed and then are
  immediately used in the next instruction
• May be STALLED by other resources not providing
  the necessary information

9
Processor architecture -- SISD

• If the TigerSHARC (or other processor) has an
  instruction that has the same format as would be
  found on any other standard processor
• You can be pretty sure that this is a SISD
• Single data single instruction
• e.g. J1 J1 1
• XR1 R2 R3 (means XR1 XR2
  XR3)
• Blackfin R1 R2 R3
• Mototola 68K MOVE D3, D1
  ADD D2, D1

10
Processor Architecture -- SIMD

• If a simple instruction has hidden
  consequences then is probably SIMD -- single
  instruction multiple data
• TigerSHARC
• XR3 R4 R5 SISD
• XR32 R54 R76 (complicated SISD)
• R3 R4 R5 SIMD
• NOTE XR3 R4 R5 YR5 R6 R7 NOT
  SIMD
• This is an instruction line of two instructions
  not a single instruction
  MISD
• Multiple instructions each changing single
  data

11
Types of TigerSHARC instructionsConcept syntax
may not be exact

• J1 J2 J3 instruction line with
  1 instruction -- SISD
• IF JALT, D0 XR4 XR5 instruction
  line with 1 instruction that
  instruction has 2 SISD components
• IF JALT, D0 R4 R5
• IF XALT, DO R4 R5 instruction line
  with 1 instruction instruction
  with SISD and SIMD comps
• IF ALT, DO R4 R5
• instruction line with 1 instruction
  instruction with 2 SIMD comps

12
Types of TigerSHARC instructionsConcept syntax
may not be exact

• XR4 R5 R6, XR7 R9 R10
• instruction line with 1 instruction
  having two SISD components
  SHARC has this
• XR4 R5 R6 XR7 R9 R10
  instruction line with 2 SISD instructions
  meaning this is demonstrating MISD operation
• R4 R5 R6 R7 R9 R10
  instruction line with 2 SIMD instructions
  meaning this is showing MIMD mode of operation

13
Memory operations

• XR1 J0 1 instruction line 1 SISD
• XR1 J0 YR1 K0 1 instruction line 2
  SISD ? MISD
• R1 J0 1 instruction line 1 SIMDoperating
  in broadcast mode since does XR1 J0 and
  YR1 J0
• R1 L J0 1 instruction line 1 SIMDNOT
  operating in broadcast mode since does XR1
  J0 and YR1 J0 1
• XR10 LJ0 1 instruction line SISD which
  does XR0 J0 and XR1 J0 1
• R10 LJ0 1 instruction line SIMD broadcast
  mode which does XR0 J0 and XR1 J0 1
  and YR0 J0 and YR1
  J0 1

14
Misperceptions

• Turn off SIMD would be faster as in SISD would
  have to fetch smaller instruction
• If this were true, then SIMD offers no advantages
  over having two SISD
• In fact would make the processor slower to handle
  this special case therefore all instructions
  would be slower
• TigerSHARC is customized for speed, any
  instruction that would slow it down is discarded
• Thats why dont have CISC type instructions of
  moving values from memory to memory or adding
  values to memory

15
Instruction format

• Idea not exact
• Every instruction has the following format of two
  components
• What to do -- opcode
• Whom do do it on -- registers

16
Instruction format idea not exact

• Lets assume we have a processor with 16-bit
  instruction width
• XXXX XXXX 0000 1110 Opcode
  register to use
• 1100 0000 0000 1110 ? XR13 0
• 1100 0111 0000 1110 ? XR13 7
• -- I am
  an equate instruction
• --
  operating on X registers
• --
  using this immediate value
• --
  operating on THIS register

17
Instruction format Concept only -- not exact

• XXXX XXXX 0000 1110 Opcode
  register to use
• 1100 0111 0000 1110 ? XR13 7
• 1101 0111 0000 1110 ? YR13 7
• 1110 0111 0000 1110 ? XYR13 7
• 1111 0111 0000 1110 ? XYR13 7
• 11 -- I am
  an equate instruction
• 00
  -- operating on X register -- SISD
• 01
  -- operating on Y register SISD
• 10
  -- operating on X and Y -- SIMD
• 11
  -- operating on pairs of X and Y -- SIMD
• --
  using this immediate value
• --
  operating on THIS register

18
Instruction format Concept only -- not exact

• XXXX 0011 0000 1110
• Opcode register to use
• 1000 0011 0000 1110 ? XR13 J0
• 1001 0011 0111 1110 ? J7 XR13 -- bit
  controlling direction
• 1010 0011 0000 1110 ? XR13 K0
• 1011 0011 0111 1110 ? K7 XR13
• 1011 1011 0111 1110 ? K7 K3 XR13
• 10 -- I am
  memory move instruction
• 00
  -- using J IALU for reads
• 01
  -- using J IALU for write
• 10
  -- using K-IALU for reads
• 11
  -- using K-IALU for writes
• 0
  -- offset 0
• 1
  -- use another I-ALU register as offset
• 
  -- which other I-ALU register to use as offset
• --
  which I-ALU to use as the primary register
• --
  which Compute register to use as source or
  destination

19
Instruction format Concept only -- not exact

• 0111 0011 1000 1110 Opcode is only 1
  bit
• I am a simultaneous multiplication,
  add and subtract SIMD
• Multiply any one of
  registers XYR0 to XYR3 with any one of registers
  XYR0 to XYR3 and store result in any one of
  registers XYR0 to XYR7
• Use this register for
  storing the add result
• Use this register
  for storing the subtract result
• Use this
  register as one of add / subtract sources
• Use this
  as the other
• XYR7 R0 R3, XYR2 R3 R2, XYR0 R3 R2
• COMMAS as all
  part of 1 instruction
• BLACKFIN SYNTAX EQUIVALENT -- in parallel with
• XYR7 R0 R3 XYR2 R3 R2 XYR0
  R3 R2

20
XR5 5.0 -- A 64-bit instruction is fed into
the instruction pipeline

• XR5 5.0R7 R5 R4 -- does NOT stall
  because of a memory fetch (data or otherwise)

which register opcode value
21
R6 0 FR4 R5 R6Is it invalid?

• Student says invalid instruction since R6 is
  being forced to store both an integer value and
  to be used as float
• Correct answer R6 is used as a storage box
  bit pattern the register does not care what
  format
• In first part of the instruction line, the bit
  pattern 0 (the same bit pattern as 0.0) is being
  stored into R6
• In the second part of the instruction line, the
  old bit pattern stored in R6 is fetched to be
  used in the floating point operation

22
FooFunction(float carPrice) sum
carPricecount

• WHY CANT THE ANSWER BE?
• temp_XR9 XR4 count_J0 sum_XR10
  R10 R9
• Need to understand the TigerSHARC architecture
• XR and YR registers are hooked to the data
  busses and not to address busses so can be
  used as a destination of a memory operations
  NOT as a pointer
• WHY DID THE CONFUSION OCCUR??
• I dont know perhaps because MIPs registers
  (from a previous course) are attached to both
  data and address busses and could be used in this
  way

23
DEFECT AVOIDANCECan one function affect another?

• loop_counter_J0 0
• loop_max_value_J25 0x12345
• lc0 35 // hardware loop counter
• J26 J26 16
• JSP JSP 24
• CALL AnotherFunction
• J0 what ???? On returning from the
  subroutine
• J25 what ????
• J26 what ????
• JSP what ????
• lc0 what???
• What registers do I to restore before
  doing implying what should I store before
  changing
• CJUMP (ABS)

24
Defect avoidance

• You must save all registers that other functions
  are relying on
• If you always save every register, you lose speed
  of operation
• MUST COMPROMISE CONVENTION
• Convention means agreed upon usage, may not be
  best for all purpose

25
Examples of conventions

• Registers J4, J5, J6 and J7 WILL be used to pass
  pointers and integers, but use XR4, XR5, XR6 and
  XR7 if using floats
• J8 WILL be used to return parameters from
  subroutines (XR8 for floats)
• For speed reasons -- Most registers on the
  TigerSHARC are immediately available for use no
  need to save before use
• Consequence if you want to retain a value in a
  register after a subroutine call most likely
  need to save the value onto the stack before
  calling the subroutine, and recover from stack
  after returning from the subroutine
• Need to understand the use of the TigerSHARC
  stack (J26) and frame-pointer registers (J27) in
  order to be able to use stack.
• J26 and J27 are NON-VOLATILE (defined) registers
  and MUST be restored
• For speed reasons, TigerSHARC stack and frame
  pointers have an unusual usage pattern

26
DEFECT AVOIDANCECan one function affect another?

• loop_counter_J0 0
• SAVE J25 to stack
• loop_max_value_J25 0x12345
• lc0 35 // hardware loop counter
• J26 J26 16
• JSP JSP 24
• CALL AnotherFunction
• J0 what ???? UNDEFINED AFTER SUBROUTINE
  CALL
• J25 what ???? PRESERVED BY CONVENTION
  if used in subroutine must be restored
• J26 what ???? PRESERVED BY CONVENTION
  -- SAME AS JSP
• JSP what ???? PRESERVED BY CONVENTION --
  SAME AS JSP
• lc0 what??? NOT PRESERVED HIDDEN
  ISSUE LIKELY DEFECT
  USE SOFTWARE LOOP
• J26 J26 24
• J26 J26 16
• RECOVER J25 from stack
• CJUMP (ABS)

27
Adjusting the stack

• Will discuss another day
• Reminder guest speaker on Tuseday