DGEI

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Building Real Integrated Circuits
Etienne SICARD INSA Toulouse
March 2007
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Introduction

• Microwind is optimized for block design, not IC
  design
• Microwind only handles up to 1000 devices
• Only the basic design rules are verified
• Weak link to foundries rule files include
  average parameters
• However, real ICs can be fabricated from
  Microwind-designed blocks
• Need to interface to CADENCE, MENTOR
• Need time, patience
• Need money for IC manufacturing, board design,
  tests
• Need a close interaction to foundry
• Confidentiality issues
• Very exiting experience

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Typical Design Cyle 15 months
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Create layout (MOS, resistor, inductor,
capacitor, interconnects)
Layout library
Main design rules

• Verify compliance to basic design rules
• Verify basic functions
• Verify performances
• Verify testability

Verify layout by simulation
Model library
Translate into CIF, GDS2
Microwind3
Import CIF, GDS2 into Cadence
I/O library

• Convert into a manufacturable design
• Create pad-ring
• Add logo

Complete Design rules
Global design rule checker

• Veriy the final circuit
• Check Supply connections
• Generate statistics
• Generate the bonding diagram

Generate final GDS2
Cadence, Mentor, etc
Send to foundry
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CIF Interface
cif nwell 1 0.0 cif diffp 17 0.25 cif diffn 16
0.25 cif aarea 2 0 cif poly 13 0.0 cif contact
19 0.025 cif metal 23 0 cif via 25 0.075 cif
metal2 27 0 cif via2 32 0.075 cif metal3 34
0 cif via3 35 0.075
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CIF Interface

• Need for over-etch to generate implant and active
  area

Nimplant
N diffusion
Active area
CIF conversion
Overetch
P diffusion
Pimplant
Active area
CIF conversion
Overetch
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Alfa2 Project

• Alfa2 test-chip CMOS 0.18µm technology (2003)
  successfully tested in 2005.
• The chip included innovative on-chip random
  sampling for measuring susceptibility to
  mobile-phone interference.
• Critical basic cells have been designed and
  simulated using Microwind version 2.7.

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Alfa2 project
MOS designed by Microwind, under CADENCE
IC and package
Result example obtained on the Alfa2 test-chip
during EMC measurements
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Biomi2

• Biomi2 test-chip has been designed, fabricated in
  a CMOS 0.8 µm technology (1999) and successfully
  tested in 2000.
• The chip included a programmable pulse generator.
  The logic design has been fully conducted using
  Dsch v2.
• The layout has been compiled in Verilog by
  Microwind v2, converted into CIF for final
  verification using professional tools.

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Biomi2
Layout compiled from VERILOG
Measured pulse waveform
Test board
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Recent project - VSM

• Very Simple Microprocessor (4-bit processor, 2000
  devices) INSA, Univ South Australia, Pa

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Recent projects - VSM
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Recent project VSM
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How will you make it

• Europractice in Europe
• MOSIS in USA
• SCL in India
• Acces to 0.8µm down to 65nm CMOS technologies

SCL in India
90 nm test-chip