Title: Minimum Dynamic Power CMOS Circuits
1Minimum Dynamic Power CMOS Circuits
- Vishwani D. Agrawal
- Rutgers University, Dept. of ECE
- Piscataway, NJ 08854
- http//cm.bell-labs.com/cm/cs/who/va
- Collaborators M. L. Bushnell and T. Raja,
Rutgers University - (Support from NSF)
2Power in a CMOS Gate
VDD 5V
IDD
Ground
3Problem Statement
- Design a digital circuit for minimum transient
energy consumption by eliminating hazards
Ref Agrawal (97), Agrawal et al. (99)
4Theorem 1
- For correct operation with minimum energy
consumption, a Boolean gate must produce no more
than one event per transition
Ref Agrawal, et al., Proc. VLSI Design99
5Theorem 2
- Given that events occur at the input of a gate
(inertial delay d ) at times t1 lt . . . lt tn ,
the number of events at the gate output cannot
exceed
tn t1 -------- d
min ( n , 1 )
tn - t1 d
time
t1 t2 t3 tn
tn d
6Minimum Transient Design
- Minimum transient energy condition for a Boolean
gate
ti - tj lt d
Where ti and tj are arrival times of
input events and d is the inertial delay of
gate
7Linear Program (LP)
- Variables gate and buffer delays
- Objective minimize number of buffers
- Subject to overall circuit delay
- Subject to minimum transient condition for
multi-input gates - AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)
8Limitations of This LP
- Constraints are written by path enumeration.
- Since number of paths in a circuit is exponential
in circuit size, the formulation is infeasible
for large circuits. - Example c880 has 6.96M constraints.
9A New LP Model
- Introduce two new variables per gate output
- ti Earliest time of signal transition at gate i.
- Ti Latest time of signal transition at gate i.
t1, T1
ti, Ti
. . .
tn, Tn
Ref Raja et al. (03)
10New Linear Program
- Gate variables d4 . . . d12
- Buffer Variables d15 . . . d29
- Corresponding window variables t4 . . . t29 and
T4 . . . T29.
11Multiple-Input Gate Constraints
For Gate 7
t5d7
T5d7
Input windows
Output windows
t5
T5
t6d7
T6d7
t6
T6
t7
T7
- T7 gt T5 d7 t7 lt t5 d7 d7 gt T7 - t7
- T7 gt T6 d7 t7 lt t6 d7
12Single-Input Gate Constraints
Buffer 19
13Overall Delay Constraints
- T11 lt maxdelay
- T12 lt maxdelay
14Why New Model is Superior?
- Path constraints from old model
- 2 2 2 2n paths between an I/O pair
- For new model, a single constraint per PO
controls I/O delay. - For new model, number of minimum energy
constraints for each gate depends on gate inputs.
15Comparison of Constraints
6.96x106
Number of constraints
3,611
c880
Number of gates in circuit
16Results 1-Bit Adder
17Estimation of Power
- Circuit is simulated by an event-driven simulator
for both optimized and un-optimized gate delays. - All transitions at a gate are counted as
Eventsgate. - Power consumed ? Eventsgate x of fanouts.
- Ref Effects of delay model on peak power
estimation of VLSI circuits, Hsiao, et al.
(ICCAD97).
18Original 1-Bit Adder
Color codes for number of transitions
19Optimized 1-Bit Adder
Color codes for number of transitions
20Benchmark Circuits
Circuit C432 C880 C6288 c7552
Maxdel. (gates) 17 34 24 48 47 94 43 86
Normalized Power
No. of Buffers 95 66 62 34 294 120 366 111
Average 0.72 0.62 0.68 0.68 0.40 0.36
0.28 0.26
Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.24
0.22
Corrected data
21Results 4-Bit ALU
maxdelay Buffers inserted
7 5
10 2
12 1
15 0
Power Savings Peak 33 , Average 21
22Physical Design
Gate l/w
Gate l/w
Gate l/w
Gate l/w
Gate delay modeled as a linear function of gate
size, total load capacitance, and fanout gate
sizes (Berkelaar and Jacobs, 1996). Layout
circuit with some nominal gate sizes. Enter
extracted routing delays in LP as constants and
solve for gate delays. Change gate sizes as
determined from a linear system of
equations. Iterate if routing delays change.
23Power Dissipation of ALU4
1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random
vectors simulated in Spice
7
6
5
Original ALU delay 3.5ns
4
Energy in nanojoules
3
Minimum energy ALU delay 10ns
2
1
0
0.0
0.5
1.5
2.0
1.0
microseconds
24ALU Original and Optimized
25References
- R. Fourer, D. M. Gay and B. W. Kernighan, AMPL A
Modeling Language for Mathematical Programming,
South San Francisco The Scientific Press, 1993. - M. Berkelaar and E. Jacobs, Using Gate Sizing to
Reduce Glitch Power, Proc. ProRISC Workshop,
Mierlo, The Netherlands, Nov. 1996, pp. 183-188. - V. D. Agrawal, Low Power Design by Hazard
Filtering, Proc. 10th Intl Conf. VLSI Design,
Jan. 1997, pp. 193-197. - M. Hsiao, E. M. Rudnick and J. H. Patel, Effects
of Delay Model in Peak Power Estimation of VLSI
Circuits, Proc. ICCAD, Nov. 1997, pp. 45-51. - V. D. Agrawal, M. L. Bushnell, G. Parthasarathy
and R. Ramadoss, Digital Circuit Design for
Minimum Transient Energy and Linear Programming
Method, Proc. 12th Intl Conf. VLSI Design, Jan.
1999, pp. 434-439. - V. D. Agrawal, Low Power Circuits Through Hazard
Pulse Suppression, US Patent 5,983,007, Nov. 9,
1999. - T. Raja, V. D. Agrawal and M. L. Bushnell,
Minimum Dynamic Power CMOS Circuit Design by a
Reduced Constraint Set Linear Program, Proc.
16th Intl Conf. VLSI Design, Jan. 2003.
26Conclusion
- Obtained an LP constraint-set that is linear in
the size of the circuit. LP solution - Eliminates glitches at all gate outputs,
- Holds I/O delay within specification, and
- Combines path-balancing and hazard-filtering to
minimize the number of delay buffers. - New LP produces results exactly identical to old
LP requiring exponential constraint-set. - Results show peak power reduction up to 78 and
average power savings up to 74.