Datapath and Control Ch 5

1
Datapath and Control (Ch 5)
2
CPU organization

• Datapath and control
• how to decide the datapath?
• What resources do we need in the datapath?
• A datapath for Ultra-8
• PC, IR, MDR, GPRs
• MUXes at ALU inputs, why?
• ALU
• MUX for memory address selection
• buffers at output of register file
• buffer at ALU output, why?

3
CPU registers

• IR, PC, MDR
• where does each get its data input?
• how do we use each of its contents?
• control signals needed to actuate each?
• GPR or register file
• external interface?
• internal logic?
• data input?
• load vs. arithmetic instructions
• control signals needed?

4

• Why do we need muxes at ALU input?
• ALU
• arithmetic instructions
• where are the operands in Ultra-8?
• address calculations
• what instructions need this? where are the
  operands?
• PC management
• what is involved in this?
• Why mux for memory address selection?
• instruction vs. data fetch (remember 12-bit
  address in Ultra-8)
• Why buffer at output of register file?
• Why buffer at output of ALU?

5
Control Design

• What is involved in instruction execution?
• fetch, decode, execute, fetch operands, store
  operands
• designing the control unit
• given instruction set, and DP
• write flowcharts this is no different from
  writing C code!
• adopt a control regime
• hardwired
• FSM
• microprogrammed control
• stored program

6
Hardwired Control

• What states do we need in the FSM?
• Actions during instruction fetch - F1
• PC to memory address
• increment PC
• gate memory data into IR(7-0)
• F2
• PC to memory address
• increment PC
• gate memory data into IR(15-8)
• control signals to be generated in F1 and F2?
• Edge-triggered clocking regime

7

• Instruction decode and register fetch - IDRF
• op code?
• Fields of IR for register fetch (R-type Ultra-8)
• can we fetch registers before decode?
• Control signals generated in IDRF?
• Write buffers at register file outputs
• next state determination based on decode
• what next?
• 5 different FSM sequences depending on
  instruction type
• R-type, M-type, I-type, J-type, O-type

8

• R-type FSM
• ALU op store result in ALUout
• write ALUout into register file
• can both the above steps be done in 1 clock?
• Where do we go from here?

9

• M-type FSM load/store
• address arithmetic result into ALUout
• ALUout to memory address bus
• load
• memory data returned into MDR
• MDR to register file
• store
• GPR at Rc field of IR to memory data bus
• when should we do this?
• back to F1

10

• M-type FSM BEQ
• ALUop using A and B buffers
• if equal
• then PCoffset to ALUout
• ALUout to PC
• else nothing
• back to F1

11

• I-type
• IR(7-0) to register specified in Rc of IR
• back to F1

12

• J-type FSM JALR
• PC to register Ra specified in IR
• contents of register Rc in IR to PC
• back to F1
• J-type FSM XFER
• Ra to ALUout
• ALUout to Rc
• back to F1

13

• O-type FSM HALT
• Quiesce state
• O-type FSM NOP
• back to F1