Simple Sequential Circuits in VHDL

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Simple Sequential Circuits in VHDL
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Contents

• Sequential circuit examples
• - SR latch in dataflow style
• - D flip-flop in behavioral style
• - shift register (8-bit) in behavioral style

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Definition of an SR latch Using Dataflow

• library IEEE
• use IEEE. std_logic_1164.all
• entity SRlatch is
• port (S,R in std_logic - - SR latch
  control inputs.
• Q, QN out std_logic) -- outputs.
• end SRlatch
• -- Dataflow. No processes or components.
• architecture SRlatch_arch1 of SRlatch is
• -- recall that all of the following are
  executed in parallel.
• begin
• QN lt S nor Q -- a change in S or Q
  executes the command.
• Q lt R nor QN -- a change in R or QN
  executes the command.
• end SRlatch_arch1 -- terminate execution when
  there are no more changes.

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D flip-flop in Behavioral Style (I/II)

• library IEEE
• use IEEE.std_logic_1164.all
• entity VposD is
• port (CLK, CLR, D in std_logic -- inputs, D
  specifies what needs to be stored
• Q, QN out std_logic) --
  flip-flop contents
• end VposDff
• -- for behavioral style, use a process.
• architecture VposDff_arch of VposDff is
• begin
• process (CLK, CLR) begin -- execution if there
  is a change in CLK or CLR
• if CLR'1' then Qlt'0' QNlt'1' --
  asynchronous CLR.
• elsif CLK' event and CLK'1' then QltD
  QNltnot D -- changes at rising edges
• end if
• end process
• end VposDff_arch

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D flip-flop in Behavioral Style (II/II)

• Here is a simplified version
• process -- without a sensitivity list, it will
  always be executed
• -- recall that the following are
  executed serially (as in "C)
• wait until CLK'1'
• Qlt D
• end process
• Or for an even simpler implementation, we include
  the following line in an
• architecture definition, where everything is
  executed in parallel
• Qlt D when CLK' event and CLK'1' else Q
• where everything has been defined as of type
  std_logic.

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Shift-register in Behavioral Style

• (Wakerly, p. 742)
• library IEEE
• use IEEE.std_logic_1164.all
• -- Use processes for behavioral style
• -- CLK defines the clock. All changes occur at
  the rising edges.
• -- S selects the function to be executed
• -- D stores the information that we would
  like to load.
• -- Q contains the register contents.
• entity Vshftreg is define inputs and outputs to
  the register
• port (CLK, CLR, RIN, LIN in STD_LOGIC --
  Clock, clear, shift bits in/out
• S in STD_LOGIC_VECTOR (2 downto 0)
  -- select function
• D in STD_LOGIC_VECTOR (7 downto 0)
  -- load data
• Q out STD_LOGIC_VECTOR (7 downto 0)) --
  register contents
• end Vshftreg

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• ?rchitecture Vshftreg_arch of Vshftreg is
• signal IQ STD_LOGIC_VECTOR (7 downto 0)
  local signal variables
• begin
• process (CLK, CLR, IQ) execution if there is a
  change in CLK, CLR, IQ
• begin -- internally, all commands are executed
  serially (as in "C").
• if (CLR'1') then IQ lt (othersgt'0') --
  Asynchronous clear
• elsif (CLK gt 'event and CLK'1') then --
  load at the rising edge
• case CONV_INTEGER(S) is
• when 0 gt null --Hold
• when 1 gt IQ lt D --Load
• when 2 gt IQ lt RIN IQ (7 downto 1) --Shift
  right
• when 3 gt IQ lt IQ(6 downto 0) LIN --Shift
  left
• when 4 gt IQ lt IQ(0) IQ(7 downto 1)--Shift
  circular right
• when 5 gt IQ lt IQ(6 downto 0) IQ(7)--Shift
  circular left
• when 6 gt IQ lt IQ(7) IQ(7 downto 1)--Shift
  circular right
• when 7 gt IQ lt IQ(6 downto 0) '0' --Shift
  circular left
• when others gt null
• end case
• end if