VHDL???? - PowerPoint PPT Presentation

1 / 152
About This Presentation
Title:

VHDL????

Description:

Title: VHDL Author: xyj Last modified by: shizi Created Date: 11/28/2001 2:11:21 PM Document presentation format: 35 Company – PowerPoint PPT presentation

Number of Views:102
Avg rating:3.0/5.0
Slides: 153
Provided by: xyj5
Category:
Tags: vhdl | fifo | vhdl

less

Transcript and Presenter's Notes

Title: VHDL????


1
VHDL????
  • ?VHDL?????????????

2
VHDL????
  • VHDL??
  • VHDL?????
  • VHDL???????

3
????
  • VHDL ??

4
VHDL???
  • VHSIC (Very High Speed Integrated Circuit)
  • Hardware
  • Description
  • Language

5
VHDL??
  • 1982?, ???????????VHSIC??
  • 1987??,VHDL?IEEE?????????????????
    ,?IEEE-1076(??87?)
  • 1993?,IEEE?VHDL?????,???????VHDL,?IEEE???1076-1993
    (1164)??
  • 1996?,IEEE-1076.3??VHDL????

6
VHDL??
  • ????????????,VHDL???????????
  • VHDL???????????,??????????????????????,???????????
    ?
  • VHDL?????????????????????????????????????????
  • ???VHDL??????????,????EDA???????????,?????VHDL????
    ???????
  • VHDL?????????????,????????????,???????????????????
    ,????????

7
VHDL???HDL??
  • VHDL???????????,?????????????????
  • Verilog?VHDL??
  • ABEL?AHDL????????????,??????????

8
???????
9
???????
10
????
  • VHDL?????

11
VHDL?????
  • Entity(??)???????????????
  • Architecture(???)????????????
  • ??????????????????,??????????

12
??
  • ??????,?????????????

13
????
  • ENTITY black_box IS
  • Generic ( constant width integer 7)
  • PORT (
  • clk, rst IN std_logic
  • d IN std_logic_vector(width DOWNTO 0)
  • q OUT std_logic_vector(width DOWNTO 0)
  • co OUT std_logic)
  • END black_box

14
Generic
  • ???? ????????,????????????????????
  • ?????,???????????????????????
  • ???????Integer?Time
  • ??????????????????

15
PORTS
  • ??(PORT)???????
  • PORT ????????,?????????
  • PORT ??? Name, Mode, ? Type
  • ??????PORT(SIGNAL NameMode Type
    BUS ??? , )

16
????
  • IN ???????????
  • OUT ???????????
  • INOUT ????????????
  • BUFFER?????????,????????

17
????
  • BIT ???,????? 0? '1
  • BIT_VECTOR ?????,???????
  • BOOLEAN????,???? TRUE?FALSE
  • INTEGER??,???-214783647?214783647(232),???,??????
    ????????????????????????????
  • Natural?????,??????,??????
  • Positive?????,??????,????????
  • REAL????,???-1.0E38?1.0E38???????????

18
????
  • ?????????????? TYPE traffic_light IS (red,
    yellow,green ) TYPE int IS RANGE 0 TO 100
  • ??????????????,???????????
  • TYPE Bit_Vector IS ARRAY (Natural RANGEltgt) OF
    Bit
  • TYPE Word IS ARRARY (31 downto 0) OF Bit
  • SUBTYPE???,?????????????? SUBTYPE Std_Logic IS
    resolved Std_Ulogic
  • TIME????,???????,???????????????????fs?ps?ns?us?
    ms?sec?min?hr???????

19
????
  • ????
  • TYPE Month_Name IS (Jan,Fab,Mar,Apr,May,Jun,Jul,A
    ug,Sep,Oct,Nov,Dec)
  • TYPE date IS RECORD
  • day Integer RANGE 1 TO 31
  • month Month_Name
  • year Integer RANGE 0 to 3000
  • END RECORD
  • VARIABLE today date
  • today (15, may, 1995)

20
Std_Logic????
  • IEEE 1164??????????,???9??????U ???? ????X
    ??? ????0 ?0 ???????1 ?1 ???????
    Z ?? ???????W ??? ????L ?0 ???????
    H ?1 ???????_ ?? ???????

21
Std_Logic????
  • ?????????????????
  • ????VHDL??????????????
  • ????????STD_LOGIC? STD_LOGIC_VECTOR ???? BIT ?
    BIT_VECTOR
  • ?????????(Z) ???STD_LOGIC ? STD_LOGIC _VECTOR
  • ??????????????????????? LIBRARY ieee
  • USE ieee.std_logic_1164.ALL

22
???
  • ?????????????
  • ?? D ?12?????
  • ?? OE ? CLK ??1???
  • ?? AD ? 12?????
  • ?? A?12?????
  • ?? INT ?1???
  • ?? AS ??????????????

23
?????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY my_design IS PORT (
  • d IN std_logic_vector(11 DOWNTO 0)
  • oe, clk IN std_logic
  • ad INOUT std_logic_vector(11 DOWNTO 0)
  • a OUT std_logic_vector(11 DOWNTO 0)
  • int OUT std_logic
  • as BUFFER std_logic)
  • END my_design

24
???
  • ????????????????
  • ?????(ENTITY)???
  • ????(ENTITY)????????
  • ??????????
  • ????????? ???? ???? ????

25
???????????
Input 1
Output 1
??
Input n
Output n
A B C D Sel
MUX_Out
2
26
??????
27
?????????
  • 2 X 8 Input AND gate
  • ENTITY black_box IS PORT (
  • a, b IN std_logic_vector(7 DOWNTO 0)
  • y OUT std_logic_vector(7 DOWNTO 0))
  • END black_box
  • ARCHITECTURE example OF black_box IS
  • BEGIN
  • y lt a AND b
  • END example

28
??????
  • ??????????
  • ???????,??????
  • ?????????????????????????
  • ????????
  • ???CONSTANT?
  • CONSTANT Width Integer 8

29
????-??
  • ??????????????
  • ?lt??????
  • SIGNALSIGNAL Count Bit_Vector(3 downto 0) IF
    Rising_Edge(clk) THEN CountltCount1 END IF
  • ???Package?Entity?Architecture ???

30
????-??
31
????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • ENTITY simp IS
  • PORT(a, b, c, d IN Std_Logic
  • g OUT Std_Logic)
  • END simp
  • ARCHITECTURE logic OF simp IS
  • SIGNAL e,f Std_Logic
  • BEGIN
  • e lt a or b
  • fltnot(c or d)
  • g lte and f
  • END logic

32
????
  • SIGNAL temp Std_Logic_Vector (7 downto 0)
  • ????temp lt 10101010temp lt xAA
  • ????temp(7) lt 1
  • ????
  • temp (7 downto 4) lt 1010

33
??????
  • ?????????
  • ?????????????????
  • ???????????
  • ???VARIABLE VARIABLE tmp Bit tmp1

34
????
  • ????temp 10101010temp xAA
  • ????temp(7) 1
  • ????temp (7 downto 4) 1010

35
??????????
ARCHITECTURE
36
????????
?? ??
???? lt
?? ??????? ??????
???? ??,?????????? ?????
?? ?????????? ????
37
?????
??? ?? ??? ??
? SLL ????
- ? SRL ????
? SLA ????
/ ? SRA ????
?? ROL ??????
MOD ?? ROR ??????
REM ?? ABS ????
38
?????
??? ??
??
/ ???
lt ??
gt ??
lt ????
gt ????
39
?????
??? ??
AND ?
OR ?
NAND ??
NOR ??
XOR ??
XNOR ???
NOT ?
40
?????
??? ??
?
- ?
??
41
?????
  • ABS NOT
  • / MOD REM
  • ? -?
  • -
  • SLL SLA SRL SRA ROL ROR
  • lt lt gt gt
  • AND OR NAND NOR XOR XNOR

?
?
42
????
  • ????????,???????????????
  • ????????????
  • ????IEEE .1164??????????LIBRARY IEEEUSE
    IEEE_Std_Logic_1164.allUSE IEEE_Std_Logic_Arith.
    allUSE IEEE_Std_Logic_unsigned.allUSE
    IEEE_Std_Logic_signed.all

43
????
????1
???
signal
????2
signal
????3
44
????
  • VHDL????????????????
  • ???????,?????????????????????????????????????????
    ????????
  • ????????????????????,?????????,??????????????
  • ????,?????????????,???????????????????(??????)?
  • ?????????????????????????,???????(????)???????(???
    ??)?

45
?????
  • VHDL????????????
  • AND, OR, NOT, XOR, XNOR, NAND
  • ? x lt(a AND NOT(s(1)) AND NOT(s(0))) OR
  • (b AND NOT(s(1)) AND s(0)) OR
  • (c AND s(1) AND NOT(s(0))) OR
  • (d AND s(1) AND s(0))
  • y lt a OR b OR c

46
With_Select_Then??????
  • ???WHEN????????
  • ??? When Others??????????
  • ???????????? (lt)
  • ?????????,???????
  • WITH selection_signal SELECT
  • signal_name lt value_1 WHEN value_a,
  • value_2 WHEN value_b,
  • ...
  • value_n WHEN value_n,
  • value_x WHEN OTHERS

47
With_Select_Then????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • ENTITY cmpl_sig IS
  • PORT ( a, b,c,d,s IN STD_LOGIC
  • x OUT STD_LOGIC)
  • END cmpl_sig
  • ARCHITECTURE logic OF cmpl_sig IS
  • BEGIN
  • WITH s SELECT
  • x lta WHEN 00, b WHEN 01,
  • c WHEN 10,
  • d WHEN OTHERS

48
With_Select_Then????
  • ??WHEN??????????
  • WITH s SELECT
  • x lt a WHEN 000 001 010,
  • b WHEN "101" "111",
  • c WHEN OTHERS

49
When_Else??????
  • ???????????,??????????
  • ?????????????????
  • ???? ELSE?????????????
  • ???????????,?????????signal_name lt value_1 WHEN
    condition1 ELSE
  • value_2 WHEN condition2 ELSE
  • ...
  • value_n WHEN conditionn ELSE
  • value_x

50
When_Else????
  • x lt a when (s 00) else
  • b when (s 01) else
  • c when (s 10) else
  • d

51
When_Else????
  • j lt w when (a 1) else
  • x when (b 1) else
  • y when (c 1) else
  • z when (d 1) else
  • 0

52
????
  • VHDL???????,?????????????
  • ??????????????
  • ????????????????
  • ???????????????????????????
  • ???????? PROCESS (?????)
    ISlt???gtBEGINlt????gtEND PROCESS ????

53
????
54
?????
  • ?????????????????????????,??????,???????????
  • ??VHDL???,???,??????????????????????????,?????????
    ????????????????
  • ????????????????????,????????????????????

55
????
  • ??????????(?????)????????????????
  • ???????????(Process) ???(Funcation)???(Procedure)?
  • ?????????????????????????????????????????

56
??????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • ENTITY if_case IS PORT
  • ( a, b, c, d IN Std_Logic
  • sel IN Std_Logic_Vector(1 downto 0)
  • y, z OUT Std_Logic)
  • END if_case
  • ARCHITECTURE logic OF if_case IS
  • BEGIN
  • if_label PROCESS(a, b, c, d, sel)
  • BEGIN
  • IF sel"00" THEN y lt a
  • ELSIF sel"01" THEN y lt b
  • ELSIF sel"10" THEN y lt c
  • ELSE y lt d
  • END IF
  • END PROCESS if_label

case_label PROCESS(a, b, c, d, sel)BEGINCASE
sel ISWHEN "00" gtz lt aWHEN "01" gtz lt
bWHEN "10" gtz lt cWHEN "11" gtz lt dWHEN
OTHERS gtz lt '0'END CASEEND PROCESS
case_labelEND logic
57
?????
  • latchlabel PROCESS(oe)
  • BEGIN
  • IF oe1 THEN
  • y lt a
  • END IF
  • END PROCESS if_label

58
?????
  • latchlabel PROCESS(oe,a)
  • BEGIN
  • IF oe1 THEN
  • y lt a
  • END IF
  • END PROCESS if_label

59
????????
Begin if en'1' then V1'1' V2'1' s1lt'1'
s2lt'1' t(0)ltv1 t(1)ltv2 t(2)lts1 t(3)lts2
v1'0' v2'0' s2lt'0' t(4)ltv1 t(5)ltv2
t(6)lts1 t(7)lts2 end if End
process yltt end
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • ENTITY ttt1 IS PORT
  • (en in std_logic
  • y OUT Std_Logic_vector(0 to 7))
  • END ttt1
  • ARCHITECTURE logic OF ttt1 IS
  • SIGNAL s1,s2 Std_logic
  • SIGNAL tStd_Logic_vector (0 to 7)
  • BEGIN
  • PROCESS(s1,s2,en)
  • Variable v1,v2Std_logic

60
????????
61
????????
  • ARCHITECTURE reg1 OF reg1 IS
  • SIGNAL a, b BIT
  • BEGIN
  • PROCESS (clk)
  • BEGIN
  • IF rising_edge(clk) THEN
  • a lt d
  • b lt a
  • q lt b
  • END IF
  • END PROCESS
  • END reg1

62
????????
  • ENTITY reg1 IS PORT ( d in BIT
  • clk in BIT
  • q out BIT)
  • END reg1
  • ARCHITECTURE reg1 OF reg1 IS
  • SIGNAL a, b BIT
  • BEGIN
  • PROCESS (clk)
  • BEGIN
  • IF rising_edge(clk) THEN
  • a lt d
  • b lt a
  • END IF
  • END PROCESS
  • q lt b
  • END reg1

63
????????
  • ENTITY reg1 IS PORT ( d in BIT
  • clk in BIT
  • q out BIT)
  • END reg1
  • ARCHITECTURE reg1 OF reg1 IS
  • VARIABLE a, b BIT
  • BEGIN
  • PROCESS (clk)
  • BEGIN
  • IF rising_edge(clk) THEN
  • a lt d
  • b lt a
  • q lt b
  • END IF
  • END PROCESS
  • END reg1

64
???????????
  • ???IF??????,???????????,???????
  • ?????????,???????
  • ???????????????????,????????????

65
IF_THEN_ELSE??
  • ????????
  • ?????????,??????????????
  • ????????????TRUE?FALSE,????????????????

IF ??? Then ???? ENDIF
IF ??? THEN ???? ELSE ???? ENDIF
IF ??? Then ???? ELSIF ??? Then ????
ELSE ???? ENDIF
66
IF_THEN_ELSE??
  • mux4_1 PROCESS (a, b, c, d, s)
  • BEGIN
  • IF s 00 THEN x lt a
  • ELSIF s 01 THEN x lt b
  • ELSIF s 10 THEN x lt c
  • ELSE x lt d
  • END IF
  • END PROCESS mux4_1

67
IF_THEN_ELSE??
  • ex1 PROCESS (a, b)
  • BEGIN
  • IF a1 THEN clt0 -- if a and b are
  • END IF -- both 1 then
  • IF b1 THEN clt1 -- b has priority
  • END IF -- so c lt 1
  • END PROCESS ex1
  • ex2 PROCESS (a, b)
  • BEGIN
  • IF b1 THEN clt1 -- if a and b are
  • END IF -- both 1 then
  • IF a1 THEN clt0 -- a has priority
  • END IF -- so c lt 0
  • END PROCESS ex2

68
CASE_WHEN??
  • ???????????????????,??????????????????
  • ????????????????????
  • ?????????????????CASE?????????,????????????????O
    THERS???
  • CASE??????????????????,????????????????
  • CASE?????????,????????????????

69
CASE_WHEN??
  • mux4_1 PROCESS (a,b,c,d,s)
  • BEGIN
  • CASE s IS
  • WHEN "00" gt x lt a
  • WHEN "01" gt x lt b
  • WHEN "10 gt x lt c
  • WHEN OTHERS gt x lt d
  • END CASE
  • END PROCESS mux4_1

70
LOOP??
FOR lt?????gt IN lt??gt LOOP ???? END LOOP
  • ????
  • LOOP??
  • ???? LOOP
  • ????
  • END LOOP LOOP??

WHILE lt?????gt LOOP ???? END LOOP
NEXT LOOP?? WHEN ??
LOOP?? LOOP ???? EXIT LOOP?? END LOOP
71
LOOP????
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all ENTITY shift4
IS PORT ( shft_lft in std_logic d_in in
std_logic_vector(3 downto 0) q_out out
std_logic_vector(7 downto 0)) END
shift4 ARCHITECTURE logic OF shift4
IS BEGIN PROCESS(d_in, shft_lft) VARIABLE
shft_var std_logic_vector(7 DOWNTO 0)
72
  • BEGIN
  • shft_var(7 downto 4) "0000"
  • shft_var(3 downto 0) d_in
  • IF shft_lft '1' THEN
  • FOR i IN 7 DOWNTO 4 LOOP
  • shft_var(i) shft_var(i-4)
  • END LOOP
  • shft_var(3 downto 0) 0000
  • ELSE shft_var shft_var
  • END IF
  • q_out lt shft_var
  • END PROCESS
  • END logic

73
??????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY compare IS PORT (
  • a, b IN std_logic_vector(0 TO 3)
  • aeqb OUT std_logic)
  • END compare
  • ARCHITECTURE archcompare OF compare IS
  • BEGIN
  • aeqb lt '1' WHEN a b ELSE '0'
  • END archcompare

74
??????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY compare IS PORT (
  • a, b IN std_logic_vector(0 TO 3)
  • aeqb OUT std_logic)
  • END compare
  • ARCHITECTURE archcompare OF compare IS
  • BEGIN
  • aeqb lt NOT( (a(0) XOR b(0)) OR
  • (a(1) XOR b(1)) OR
  • (a(2) XOR b(2)) OR
  • (a(3) XOR b(3)))
  • END archcompare

75
??????
  • ARCHITECTURE archcompare OF compare IS
  • BEGIN
  • comp PROCESS (a, b)
  • BEGIN
  • IF a b THEN
  • aeqb lt '1'
  • ELSE
  • aeqb lt '0'
  • END IF
  • END PROCESS comp
  • END archcompare

76
??????
  • ARCHITECTURE archincomplete OF incomplete IS
  • BEGIN
  • im_mem PROCESS (a,b)
  • BEGIN
  • IF a '1' THEN c lt b
  • END IF
  • END PROCESS im_mem
  • END archincomplete

77
??????
  • ARCHITECTURE archcomplete OF complete IS
  • BEGIN
  • no_mem PROCESS (a, b)
  • BEGIN
  • IF a '1' THEN c lt b
  • ELSE c lt '0'
  • END IF
  • END PROCESS no_mem
  • END archcomplete

78
????????
  • ?ELSE????IF...THEN... ??
  • ?CASE??????????????CASE????WHEN OTHERS??
  • CASE select IS
  • WHEN "100" gt key lt first
  • WHEN "010" gt key lt second
  • WHEN "001" gt key lt third
  • WHEN OTHERS gt key lt none
  • END CASE

79
??????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • ENTITY dff_a IS PORT ( d in std_logic
  • clk in std_logic
  • q out std_logic)
  • END dff_a
  • ARCHITECTURE behavior OF dff_a IS
  • BEGIN
  • PROCESS (clk)
  • BEGIN
  • IF clk'event and clk '1' THEN q lt d
  • END IF
  • END PROCESS
  • END behavior

80
??????
  • ARCHITECTURE behavior OF dff_clr IS
  • BEGIN
  • PROCESS(clk, clr)
  • BEGIN
  • IF clr '0' THEN q lt '0'
  • ELSIF rising_edge(clk) THEN q lt d
  • END IF
  • END PROCESS
  • END behavior

81
??????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • USE ieee.std_logic_unsigned.all
  • upcount PROCESS (clk, rst)
  • BEGIN
  • IF rst '1' THEN count lt x"0"
  • ELSIF rising_edge(clk) THEN
  • IF load '1' THEN count lt data
  • ELSE count lt count 1
  • END IF
  • END IF
  • END PROCESS upcount

82
??????
  • ARCHITECTURE logic OF count_a IS
  • BEGIN
  • PROCESS(rst, clk)
  • VARIABLE tmp_q std_logic_vector(15 downto 0)
  • BEGIN
  • IF rst '0' THEN q lt 0
  • ELSIF rising_edge(clk) THEN
  • IF updn '1' THEN tmp_q tmp_q 1
  • ELSE tmp_q tmp_q - 1
  • END IF
  • q lt tmp_q
  • END IF
  • END PROCESS
  • END logic

83
??????
  • ENTITY test_three IS PORT(
  • oe IN std_logic
  • data OUT std_logic_vector(0 to 7))
  • END test_three
  • ARCHITECTURE archtest_three OF test_three IS
  • BEGIN
  • PROCESS (oe)
  • BEGIN
  • IF (oe'1') THEN data lt "01100100"
  • ELSE data lt "ZZZZZZZZ" END IF
  • END PROCESS
  • END archtest_three

84
?????
  • ENTITY ldcnt IS PORT ( clk, ld, oe IN
    std_logic
  • count INOUT std_logic_vector(7 DOWNTO
    0))
  • END ldcnt
  • ARCHITECTURE archldcnt OF ldcnt IS
  • SIGNAL int_count std_logic_vector(7 DOWNTO 0)
  • BEGIN
  • cnt PROCESS (clk)
  • BEGIN
  • IF rising_edge(clk) THEN
  • IF ld'1' THEN int_count lt count
  • ELSE int_count lt int_count 1
  • END IF
  • END IF
  • END PROCESS cnt

85
?????
  • outen PROCESS (oe, int_count) BEGIN
  • IF oe '1' THEN count lt int_count
  • ELSE count lt (OTHERS gt 'Z')
  • END IF
  • END PROCESS outen
  • END archldcnt

86
? ?
  • ????????????
  • ???????????????
  • ???????????????
  • ???????????
  • ???ALIASALIAS BankBit_Vector(0 to 3) IS
    Address(24 to 27)

87
?????
88
????????
  • ????????????????????4??????,????????
    ??100 ??201 ??310 ??411
  • ?????????,????,???????????????01-gt10

89
????????
  • ??????????????????? ???4??????,????????
    ??100 ??201 ??311
    ??410
  • ?????????,????,???????????????????????????,??????
    ?????

90
ONE HOT?????
  • ONE HOT??????????????????,?4????????4??????????1??
    ??????l?????4??????,?ONE HOT????
    ??10001 ??20010 ??30100
    ??41000
  • ?????????,?????,???

91
???????
  • ?????????????????????2??????????
  • ??????FPGA????ONE HOT??,CPLD????2??????????
  • ???????? ????????,??????????????????????????????
    ???????????,??????????????,???????????????

92
?????????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY state_machine IS PORT (
  • clock, reset IN std_logic
  • timer1, timer2, timer3 IN std_logic
  • r, y, g OUT std_logic)
  • END state_machine

93
????????
  • ARCHITECTURE arch_1 OF state_machine IS
  • TYPE traffic_states IS (red, yellow, green)
  • SIGNAL sm traffic_states
  • BEGIN
  • fsm PROCESS (clock, reset)
  • BEGIN
  • IF reset '1' THEN sm lt red
  • ELSIF rising_edge(clock) THEN
  • CASE sm IS
  • WHEN red gt IF timer11 THEN sm lt green
  • END IF
  • WHEN green gt IF timer21' THEN sm lt
    yellow
  • END IF

94
????????
  • WHEN yellow gt IF timer31' THEN sm lt red
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF
  • END PROCESS fsm
  • r lt '1' WHEN (sm red) ELSE '0'
  • g lt '1' WHEN (sm green) ELSE '0'
  • y lt '1' WHEN (sm yellow) ELSE '0'
  • END arch_1

95
????
96
????????
  • ARCHITECTURE arch_2 OF state_machine IS
  • TYPE traffic_states IS (red, yellow, green)
  • SIGNAL sm traffic_states
  • BEGIN
  • fsm PROCESS (clock, reset)
  • BEGIN
  • IF reset '1' THEN sm lt red rlt1 glt0
    ylt0
  • ELSIF rising_edge(clock) THEN
  • CASE sm IS
  • WHEN red gt IF timer11 THEN
  • sm lt green rlt0 glt1 y0
  • ELSE sm lt redrlt1 glt0 y0
  • END IF

97
????????
  • WHEN green gt IF timer21' THEN
  • sm lt yellow rlt0 glt0 ylt1
  • ELSE sm lt green rlt0 glt1
    ylt0
  • END IF
  • WHEN yellow gt IF timer31' THEN
  • sm lt red rlt1 glt0 ylt0
  • ELSE sm lt yellow rlt0 glt0 ylt1
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF
  • END PROCESS fsm
  • END arch_2

98
?????
99
????????
  • ARCHITECTURE arch_3 OF state_machine IS
  • SIGNAL sm std_logic_vector(2 DownTo 0)
  • Constant redstd_logic_vector(2 DownTo 0)
    100"
  • Constant green std_logic_vector(2 DownTo 0)
    "010"
  • Constant yellow std_logic_vector(2 DownTo 0)
    "001"
  • BEGIN
  • fsm PROCESS (clock, reset)
  • BEGIN
  • IF reset '1' THEN sm lt red
  • ELSIF rising_edge(clock) THEN
  • CASE sm IS
  • WHEN red gt IF timer11 THEN
  • sm lt green
  • ELSE
  • sm lt red
  • END IF

100
????????
  • WHEN green gt IF timer21' THEN sm lt yellow
  • ELSE sm lt green
  • END IF
  • WHEN yellow gt IF timer31' THEN sm lt red
  • ELSE sm lt yellow
  • END IF
  • WHEN others gt sm lt red
  • END CASE
  • END IF
  • END PROCESS fsm
  • r lt sm(2)
  • g lt sm(1)
  • y lt sm(0)
  • END arch_3

101
?????
102
VHDL ?????????
  • COMPONENTs ?????????
  • ?????????????
  • PACKAGEs ????,???????????????????????????????,???
    ????????
  • LIBRARIES ??????????????????

103
??????????
mux2to1
p
a
q
a
t
c
c
r
b
b
sel
s
sel
toplevel
mux2to1
  • schematic
  • entity/architecture
  • top level schematic
  • top level entity/architecture
  • symbol
  • component

104
???????
105
Package ?Component ??
LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY
mux2to1 IS PORT ( a, b, sel IN std_logic
c OUT std_logic) END
mux2to1 ARCHITECTURE archmux2to1 OF mux2to1
IS BEGIN c lt (a AND NOT sel) OR (b AND
sel) END archmux2to1
Entity/Architecture File (VHDL)
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • PACKAGE mymuxpkg IS
  • COMPONENT mux2to1 PORT (
  • a, b, sel IN std_logic
  • c OUT std_logic)
  • END COMPONENT
  • END mymuxpkg

Package and Component Declaration File (VHDL)
106
??????
  • LIBRARY ieee
  • USE ieee.std_logic_1164.ALL
  • ENTITY toplevel IS PORT (s IN std_logic
  • p, q, r IN std_logic_vector(2 DOWNTO 0)
  • t OUT std_logic_vector(2 DOWNTO 0))
  • END toplevel
  • USE WORK.mymuxpkg.ALL
  • ARCHITECTURE archtoplevel OF toplevel IS
  • SIGNAL i std_logic_vector(2 DOWNTO 0)
  • BEGIN
  • m0 mux2to1 PortMap (agti(2), bgtr(0), selgts,
    cgtt(0))
  • m1 mux2to1 PortMap (cgtt(1), bgtr(1), agti(1),
    selgts)
  • i lt p AND NOT q
  • END archtoplevel

107
????
  • ?MAXPLUS II???VHDL????

108
Altera VHDL
  • MaxPlus II ?? VHDL87 ?VHDL93
  • MaxPlus II ?????? IEEE ?????
  • ???????Altera?VHDL??

109
VHDL????
110
VHDL????
  • ??VHDL???

111
VHDL????
  • ??? VHDL ????? name.VHD

112
VHDL????
  • ??VHDL??????

113
VHDL????
  • ??VHDL??

114
VHDL????
?????
????????
115
VHDL????
116
??????
117
VHDL??
118
??VHDL????
?? VHDL ??
119
???????????????
120
????
  • ?VHDL?????EAB

121
??
  • ?????????????????? 011011 ??
  • ??????????1

Serial_in
Match
VHDL State Machine
clk
122
VHDL??
when state01101 gt if (serial_in '1') then
present_state lt state011011
else
present_state lt idle end
if when state011011 gt present_state lt
idle when others gt present_state lt
idle end case end if end if end
process process(present_state) begin if
(present_state state011011) then match lt
'1' else match lt '0' end if end process end
body_stmh
library ieee use ieee.std_logic_1164.all package
your_own_type is type t_state is
(idle,state0,state01,state011,
state0110,state01101,
state011011) end your_own_type library
ieee use ieee.std_logic_1164.all use
work.your_own_type.all Entity stmh is port (clk,
serial_in, reset in std_logic match
out std_logic) end stmh architecture body_stmh
of stmh is signal present_state
t_state begin process(clk,serial_in,
present_state) begin if (reset '1')
then present_state lt idle else
if (clk'event and clk'1') then case
present_state is when idle gt if
(serial_in '0') then
present_state lt state0
else present_state lt idle
end if when state0
gt if (serial_in '1') then
present_state lt state01
else present_state lt idle
end if when state01
gt if (serial_in '1') then
present_state lt state011
else present_state lt idle
end if when state011
gt if (serial_in '0') then
present_state lt state0110
else present_state lt idle
end if when
state0110 gt if (serial_in '1') then
present_state lt state01101
else present_state
lt idle end if
123
?????????
????
??????
124
?????
  • ?????
  • Idle, State0, State01, State011, State0110,
    State01101, State011011
  • ????
  • Match, State_Machine (3 bits)
  • ????
  • Serial_in, State_Machine (3 bits)
  • ????
  • ?????? DFF ????

125
????
  • ????????????

case present_state is when idle gt if
(serial_in '0') then
present_state lt state0
else present_state lt idle
end if
Input
Output
126
10K10 EAB???????
  • Input - 4 input (OK)
  • Output - 4 output (OK)
  • ?????????????
  • 24 4 64 bits lt 2Kbits (OK)
  • Input Register - Not used (OK)
  • Output Register - All used (OK)
  • Does not support RESET (Remove)
  • Feedback Path (NO)

127
EAB??
?????
128
???????
library ieee use ieee.std_logic_1164.all package
your_own_type is type t_state is
(idle,state0,state01,state011,
state0110,state01101,
state011011) end your_own_type library
ieee use ieee.std_logic_1164.all use
work.your_own_type.all Entity stmh is port (clk,
serial_in in std_logic match out
std_logic) end stmh architecture body_stmh of
stmh is signal present_state,next_state
t_state begin process(clk,serial_in,
present_state) begin
if (clk'event and clk'1') then case
present_state is when idle gt if
(serial_in '0') then
next_state lt state0 match
lt '0' else
next_state lt idle
match lt '0' end if
when state0 gt if (serial_in '1') then
next_state lt state01
match lt '0' else
next_state lt idle
match lt '0' end
if when state01 gt if (serial_in '1')
then next_state lt
state011 match lt '0'
else
next_state lt idle match lt
'0' end if when
state011 gt if (serial_in '0') then
next_state lt state0110
match lt '0' else
next_state lt idle
match lt '0' end if
when state0110 gt if (serial_in '1') then
next_state lt state01101
match lt '0'
else next_state lt idle
match lt '0'
end if when state01101 gt if (serial_in
'1') then next_state lt
state011011 match lt '1'
else
next_state lt idle match lt
'0' end if when
state011011 gt next_state lt idle
match lt '0' when others gt
next_state lt idle match
lt '0' end case end if end process present_sta
te lt next_state end body_stmh
129
????
130
??
131
????
?????????EAB?
132
??VHDL??
component stmh port (clk, serial_in in
std_logic present_state in t_state
next_state out t_state match out
std_logic) end component signal
t_state_bufferin, t_state_bufferout
t_state begin t_state_bufferin lt
t_state_bufferout u1stmh port map
(clkgtclk,serial_ingtserial_in, present_stategtt_
state_bufferin, next_stategtt_state_buf
ferout, matchgtmatch) end body_stmheab
library ieee use ieee.std_logic_1164.all package
your_own_type is type t_state is
(idle,state0,state01,state011,
state0110,state01101,
state011011) end your_own_type library
ieee use ieee.std_logic_1164.all use
work.your_own_type.all Entity stmheab is port
(clk, serial_in in std_logic match out
std_logic) end stmheab architecture
body_stmheab of stmheab is
133
??????
library ieee use ieee.std_logic_1164.all use
work.your_own_type.all Entity stmh is port (clk,
serial_in in std_logic present_state
in t_state next_state out t_state
match out std_logic) end stmh architecture
body_stmh of stmh is begin process(clk,serial_in,
present_state) begin
if (clk'event and clk'1') then case
present_state is when idle gt if
(serial_in '0') then
next_state lt state0 match
lt '0' else
next_state lt idle
match lt '0' end if
when state0 gt if (serial_in '1') then
next_state lt state01
match lt '0' else
next_state lt idle
match lt '0' end
if when state01 gt if (serial_in '1')
then next_state lt
state011 match lt '0'
else
next_state lt idle match lt
'0' end if when
state011 gt if (serial_in '0') then
next_state lt state0110
match lt '0' else
next_state lt idle
match lt '0' end if

when state0110 gt if (serial_in '1') then
next_state lt state01101
match lt '0'
else next_state lt idle
match lt '0'
end if when state01101 gt if
(serial_in '1') then
next_state lt state011011
match lt '1' else
next_state lt idle
match lt '0' end if
when state011011 gt next_state lt idle
match lt '0' when
others gt next_state lt idle
match lt '0' end case end if end
process end body_stmh
134
??
135
??
136
????
  • ?VHDL???????LPM

137
LPM(???????)
  • ????????????????,????LPM???????,???????????????
  • LPM???????????????
  • ??LPM????????,????????????????????????????????????
    ??????
  • LPM??????25?1pm??,?lpm_dff, lpm_rom, lpm_ram_dq
    etc.

138
ALTERA???LPM?
??? ??? ??? ???
??? ?? ??? ??
lpm_and ????? lpm_or ?????
lpm_inv ????? lpm_constant ????????
lpm_bustri ???????? lpm_xor ??????
lpm_mux ???????? lpm_decode ??????
lpm_clshift ?????? busmux ?????
mux ?????
139
ALTERA???LPM?
???? ????
??? ??
divide ???
lpm_compare ??????
lpm_abs ????????
lpm_counter ??????
lpm_add_sub ?????????
lpm_divide ??????
lpm_mult ??????
140
ALTERA???LPM?
??? ??? ??? ???
??? ?? ??? ??
altdpram ?????RAM scfifo ??????FIFO
lpm_latch ?????? lpm_ram_dq ?????RAM
csfifo ???????FIFO csdpram ?????RAM
lpm_shiftreg ???????? lpm_ram_io ???RAM
dcfifo ??????FIFO lpm_ff ??????
lpm_ram_dp ?????RAM lpm_rom ???ROM
lpm_fifo ???FIFO lpm_dff ???D???
lpm_fifo_dc ??????FIFO lpm_tff ???T???
141
ALTERA???LPM?
???? ????
??? ??
clklock ???
pll ?????????
ntsc NTSC???????
142
?????????LPM
  • ??
  • 1????
  • 2?ROM
  • 3?CLKLOCK

143
?VHDL????????
  • ??

144
?VHDL???LPM
  • ??
  • RAM

145
VHDL?????????
  • library ieee
  • use ieee.std_logic_1164.all
  • library lpm
  • use lpm.lpm_components.all
  • entity tri_bus is
  • port (a,b in std_logic_vector(7 downto 0)
  • aen, ben in std_logic
  • q out std_logic_vector(7 downto 0))
  • end tri_bus
  • architecture tri_bus_body of tri_bus is
  • COMPONENT lpm_bustri
  • GENERIC (LPM_WIDTH POSITIVE)
  • PORT (data IN STD_LOGIC_VECTOR(LPM_WIDTH-1
    DOWNTO 0)
  • enabledt IN STD_LOGIC '0'
  • tridata INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1
    DOWNTO 0))
  • END COMPONENT
  • signal temp std_logic_vector(7 downto 0)
  • begin
  • u1lpm_bustri

146
??????
147
?????????
148
????
149
????
150
????
151
??
152
????
Write a Comment
User Comments (0)
About PowerShow.com