RTL%20Design%20Methodology

1
Lecture 9 RTL Design Methodology
2
Structure of a Typical Digital System
Data Inputs
Control Status Inputs
Control Signals
Datapath (Execution Unit)
Controller (Control Unit)
Status Signals
Data Outputs
Control Status Outputs
3
Hardware Design with RTL VHDL
Interface
Pseudocode
Datapath
Controller
Block diagram
Block diagram
State diagram or ASM chart
VHDL code
VHDL code
VHDL code
4
Steps of the Design Process

• Text description
• Interface
• Pseudocode
• Block diagram of the Datapath
• Interface with the division into the Datapath
• and the Controller
• ASM chart of the Controller
• RTL VHDL code of the Datapath, the Controller,
  and the Top Unit
• Testbench of the Datapath, the Controller, and
  the Top Unit
• Functional simulation and debugging
• Synthesis and post-synthesis simulation
• Implementation and timing simulation
• Experimental testing

5
Steps of the Design ProcessPracticed in Class
Today

• Text description
• Interface
• Pseudocode
• Block diagram of the Datapath
• Interface with the division into the Datapath
• and the Controller
• ASM chart of the Controller
• RTL VHDL code of the Datapath, the Controller,
  and the Top Unit
• Testbench of the Datapath, the Controller, and
  the Top Unit
• Functional simulation and debugging
• Synthesis and post-synthesis simulation
• Implementation and timing simulation
• Experimental testing

6
min_max_average example
7
Circuit Interface
clk
DONE
reset
n
n
in_data
out_data
5
MIN_MAX_AVR
2
in_addr
out_addr
write
START
8
Interface Table
Port Width Meaning
clk 1 System clock
reset 1 System reset clears internal registers
in_data n Input data bus
in_addr 5 Address of the internal memory where input data is stored
write 1 Synchronous write control signal
START 1 Starts the computations
DONE 1 Asserted when all results are ready
out_data n Output data bus used to read results
out_addr 2 01 reading minimum 10 reading maximum 11 reading average
9
Pseudocode
FOR m5
FOR any m
load input data
load input data
Max 0 Min 2n-1 Sum 0 for i0 to 31 do
Max 0 Min 2n-1 Sum 0 for i0 to 2m-1 do
Sum Sum Mi if (Mi gt Min) then Min
Mi endif if (Mi lt Max) then Max Mi endif
Sum Sum Mi if (Mi gt Min) then Min
Mi endif if (Mi lt Max) then Max Mi endif
endfor
endfor
Sum Sum gtgt 5
Sum Sum gtgt m
read output data
read output data
10
sorting example
11
Sorting - Required Interface
12
Sorting - Required Interface
13
Simulation results for the sort operation
(1)Loading memory and starting sorting
14
Simulation results for the sort operation
(2)Completing sorting and reading out memory
15
Sorting - Example
During Sorting
After sorting
Before sorting
i0 i0 i0 i1 i1 i2 j1 j2 j3 j2 j3 j3
Address
0 1 2 3
3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3
1 1 1 1 2 2 3 4
Legend
position of memory indexed by i
position of memory indexed by j
Mj
Mi
16
Pseudocode
FOR k 4
FOR any k 2
load input data
load input data
for
i

0
to
2
do
A

M

i
for
j

i

1
to
3
do
B

M

j
if
B
lt
A
then
M

B

i
M

A

j
A

M

i
endif

endfor
endfor
read output data
read output data
17
Pseudocode

• wait for s1
• for i0 to k-2 do
• A Mi
• for ji1 to k-1 do
• B Mj
• if A gt B then
• Mi B
• Mj A
• A Mi
• end if
• end for
• end for
• Done
• wait for s0
• go to the beginning

18
Block diagram of the Execution Unit
19
Interface with the division into the Datapath
and the Controller
DataIn
Clock
Resetn
WrInit
s
RAddr
Rd
N
L
AgtB
Int Wr Li Ei Lj Ej EA EB Bout Csel Rdout
zi
zj
Datapath
Controller
N
DataOut
Done
20
Project SHA-3 Core Interface
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