8.1 Bipolar integrated circuits

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8.1 Bipolar integrated circuits Junction
isolated bipolar circuit In the first developed
bipolar integrated circuits, the transistors are
isolated from each other by reverse biased p-n
junctions. An n type epitaxial layer is grown on
top of a p-type substrate (for fabricating npn
transistors). A deep p diffusion in selected
areas penetrates the epi-layer, and forms islands
of n regions which are used as the collectors.
Subsequent diffusions will form the base and
emitter regions.
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Isolation diffusion
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• The isolation between collectors of adjacent
  transistors is through reverse biased junction
  diodes. A parasitic depletion layer capacitance
  and leakage current exists due to the isolating
  junction. The substrate doping should be light to
  minimize the parasitic capacitance. (5?cm-20?cm)
  The resistivity of the epitaxial layer
  (0.1?cm-10?cm) affects the collector resistance,
  collector-base junction capacitance. The
  isolation diffusion must be of high concentration
  to minimize separation between islands.

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Junction Isolation
Process sequence for junction - isolated bipolar
circuits with buried layers (a) after selective
diffusion of the n - buried layer (b) after
epitaxial layer decomposition and growth of
protective oxide (c) after isolation
diffusion (d) after drain collector
diffusion (e) after base diffusion
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• The base diffusion consists of two steps
  pre-deposition and drive-in. The emitter
  diffusion consists of only one step, because the
  emitter junction depth is low. A n diffusion is
  made for collector contacts to avoid possible
  surface inversion or Schottky barrier contact
  with aluminum.

• To reduce the large series resistance between
  the collector contact and the active collector
  region, a n buried layer is formed in the
  collector region of the substrate before
  depositing the epitaxial layer. The buried layer
  can also suppress the parasitic transistor action
  between the base, collector and substrate by
  increasing the base width of the parasitic
  transistor.

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• Local Oxide Isolation
• Local oxide isolation process eliminates
  collector-substrate capacitance by using
  thermally grown SiO2 as isolation. It results in
  higher speed because of smaller parasitic
  capacitance and device geometry.
• Silicon nitride is used to mask against the
  oxide growth. Trenches are etched in Si to a
  depth of 55 of desired oxide thickness. After
  oxidation, SiO2 will be leveled with the
  epitaxial layer, since the specific volume of
  silicon dioxide is 2.2 times that of Si. A bird's
  beak is formed at the transition between the
  recessed oxide region and the Si3O4 mask.

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8.2 MOSFET Physics 8.2.1 The MOS capacitor is
an useful structure in characterizing the
performance of MOS transistors.
VGS
SiO2
Si
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Ideal MOS electric field in MOS equal to zero
if the applied voltage VGS is zero In practice,
a flat-band voltage VFB has to be applied at the
metal to maintain zero electric field in Si, due
to (a) work function difference between metal and
Si, and (b) charges at the oxide-semiconductor
interface. Three possible conditions Accumulation
majority carriers accumulated near the Si
surface, VGSltVFB in p-type substrates Depletion
majority carriers depleted away from the surface,
VGSgtVFB in p-type substrates Inversion Si is
inverted near the surface, i.e.large
concentrations of electrons present for p-type
substrates when VGSgtgtVFB
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8.2.2 MOSFET structure
drain
gate
gate
substrate
source
drain
SiO2
source
N
N
N-channel MOSFET
P
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When the gate voltage is above the threshold
voltage, Si surface is inverted with high
concentration of electrons. The n source and
drain regions are thus connected and a channel is
formed. The gate bias can alter the electron
concentration in the channel and thus control the
drain current. In the linear region, drain
current nearly increases linearly with drain
voltage because a channel exists continuously
between source and drain. In the saturation
region where VDSgtVdsat, drain current increases
slightly with drain voltage. Two reasons (a)
pinch-off of channel near drain in long channel
devices, (b) limiting of carrier drift velocity
due to hot electron effect.
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8.2.3 Threshold Voltage VT We first determine the
flatband voltage of MOS capacitor
where ?ms ?m- ?si is the metal-semiconductor
work function difference, Nss is the interface
state density (per unit surface area) note the
minus sign in the second term because of charge
induced on the gate is opposite in sign to
interface charges
q?si q?m
Efs
Efm
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Let the Si surface potential be ?s when the gate
voltage is equal to the threshold voltage. The
surface is in strong inversion. The voltage
across the gate and Si surface is equal to
VT-VFB- ?s . Therefore the charge on the gate
(which is equal and opposite to the charge in the
Si) is equal to
where NA is the substrate doping concentration, W
is the depletion width ?s is the surface
potential given by
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Sub. in the threshold voltage gives (for
n-channel MOS)
Adjustment of threshold voltage by ion
implantation of a charge sheet Qim (per unit
area) at the Si surface The flatband voltage VFB
is modified as Qim can be ve or ve depending
on whether donors or acceptors.
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8.2.4 Current-voltage characteristics in
MOSFET Let the voltage at the channel with
respect to the source be V(x) at a point of
distance x from the source. If Qn(x) is the
channel charge (per unit surface area), Gauss law
gives
where ?ox and d are the permittivity and
thickness of oxide. Considering the drift current
only, the channel current is given by where W
is width of channel, ? is the carrier mobility
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In linear region, integrating the above equ from
source to drain,
Transconductance
Channel conductance
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In long channel MOSFET, saturation occurs when
the channel charge is zero at the drain when VDS
is increased. Solving Qn(L)0 gives the
saturation drain voltage
VDsat VGS-VT The saturation drain current
at VDat is given by
Transconductance In saturation region, ID
increases slightly with drain voltage
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8.3 MOS integrated circuits The first commercial
MOS IC was thick oxide, metal gate p-channel.
The gate oxide is between 500? to 1000A, and the
thick field oxide is about 1.5?m to maintain a
high field threshold voltage. The disadvantages
of the thick oxide process are i) a large field
oxide step exists at the source, drain regions,
which may cause problems of step coverage in the
metallisaton, ii) the diffusion and metal gate
are defined by separate masks. In order to allow
for tolerances in the photolithographic process,
an overlap between the gate and source, drain
usually exists. This results in higher
capacitance between gate and drain.
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Self-aligned polycrystalline silicon gate process
Process sequence for self-aligned polysilicon
gate NMOS circuits (a) after etching of upper
oxide to expose all regions that will not be
transistors (b) after selective growth of the
thick-field oxide and the gate oxide (c) after
deposition and patterning of the polysilicon
layer (d) after source-and-drain diffusion (e)
completed structure.
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Perspective view of an n - channel polysilicon
gate MOSFET
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(a) NMOS IC For a n-channel MOS process, a
p-type Si substrate is first thermally oxidized,
and then coated with CVD silicon nitride and
photoresist. The silicon nitride in the isolation
regions is then etched using dry etching. The
etched regions of the oxide exposes the Si area
which will subsequently be oxidized using the
local oxidation technique (to serve as the
isolation region between active transistors.)
Before this oxide is formed, a boron channel-stop
is implanted into the isolation regions. The
resist is then removed, and the field oxide is
grown. This oxidation also acts to drive in the
channel-stop implant. The nitride/pad oxide is
stripped and a thin gate oxide is formed. A
threshold-adjust implant follows.
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• The polysilicon gate is deposited and doped
  with n-type impurities. After the polysilicon
  gate is patterned, the source/drain regions are
  implanted with arsenic or phosphorus. This
  implant is self-aligned to both the gate
  polysilicon and the field oxide. This is done by
  choosing the implant energy so that the dopant
  easily penetrates the thin gate oxide left in the
  source\drain regions but will not penetrate
  either the polysilicon gate or the field oxide.
  This self-aligned feature is an important aspect
  which allows minimum possible overlap between the
  gate and source\drain regions.

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• The final part of the processing serves to form
  metal connection between the devices and provide
  protection for the devices. A CVD oxide (glass)
  doped with phosphorus is deposited on the wafer.
  The phosphorus included in the glass serves two
  purposes
• i) allows the glass to flow with low viscosity at
  low temperature and smooth the surface
  topography
• ii) protect the devices from mobile ion (Na)
  contaminations.
• The P-glass also acts as a dielectric to isolate
  the metal interconnect level from the
  polysilicon. Contact windows are etched into the
  P-glass to expose the source\drain regions or
  polysilicon wherever contacts are desired.
  Aluminum is usually the metal used to
  interconnect the devices.

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• The last layer deposited on the wafer is a
  capping layer of plasma deposited silicon nitride
  or oxide used to protect the wafer from
  scratching or contamination's. Windows are then
  etched in this capping layer to make external
  wire connections.

Design considerations i) Isolation between
active devices is usually achieved by local
oxidation process. Thick field oxide and
channel-stop implant in the isolation regions are
used to prevent surface inversion.
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ii) A shallow implant (with dopants close to
the interface) in the gate region is often used
to adjust the threshold voltage. (In n-channel
MOS, a boron implant raises the threshold
voltage, and a phosphorus implant reduces the
threshold voltage.) iii) A deep implant in the
gate region can alter the effective impurity
concentration in the channel. For example, deep
boron implant in p-type substrate is often
applied to reduce the punch through
susceptibility of short channel MOS devices.
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iv) Heavily doped n-type polysilicon is most
widely used as the gate material in NMOS.The work
function of n polysilicon is ideal for n-channel
device since it yields a threshold voltage of
0.7V for suitable values of channel doping and
oxide thickness. The major disadvantage to
using polysilicon gate is the higher gate
resistance (10?/sq) causing RC delay of signals.
Using refractory metals and silicides can reduce
the sheet resistance of gate interconnect to
about 1 ?/sq, but may cause adhesion problems
between the gate material and gate oxide. One
approach is to use a refractory metal silicide on
top of the polysilicon gate (called polycide).
Common silicides used include MoSi2, WSi2, TaSi2,
TiSi2.
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v) The n source/drain region of NMOS device
should have as low resistance as possible.
Shallow junction is also required to allow for
small dimensions in VLSI. Arsenic is used as the
dopant for source/drain since it has a s high
solubility and low diffusion rate. Aluminum
deposited on silicon is unstable even at moderate
temperatures. At 450?C, dissolution of silicon by
diffusion into Al occurs, leading to pit
formation on the Si surface. The pit growth can
lead to contact and junction failure.
Contact-failure also exists due to the
precipitation of dissolved Si from aluminum on
cooling. The silicon precipitates may cause an
undesirable increase in the contact resistance,
especially in Al-n-Si contacts.
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Al

• To prevent junction shorts caused by the
  dissolution of silicon into aluminum, some
  silicon (about 1 wt) is added to aluminum during
  the deposition. To better solve the problem of
  Al-Si interaction, a diffusion barrier is
  inserted between the Si and Al. Refractory metal
  silicides are often used as the diffusion
  barriers. This technique also allows the
  simultaneous silicidation of source, drain and
  gate.

P-Si
N-Si
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• CMOS IC
• CMOS technology employs both NMOS and PMOS
  transistors in the logic circuits. The advantage
  of CMOS is that logic elements only draw
  significant current during the transition from
  one state to another but draw very little current
  in the steady state, thus consuming very little
  power.
• The first difference in fabrication procedures
  between NMOS and CMOS is the provision of proper
  substrates for n-channel and p-channel
  transistors. There are 3 approaches called the
  p-well, n-well and twin-well processes.

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• The p-well process involves implanting or
  diffusing p-type dopants into an n-substrate at a
  concentration high enough to over-compensate the
  n-substrate and ensure proper p-channel device
  characteristics. However excessive p-well doping
  produces adverse effects in the n-channel device,
  such as increased back-gate bias effects,
  reduction in mobility, and increased source/drain
  to p-well capacitance.

• The n-well process is an alternative approach
  where an n-well is formed in a p-type substrate.
  In this case, the n-well overcompensates the
  p-substrate, and the p-channel device suffers
  from excessive doping effects.

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• The twin-well process allows two separate wells
  to be implanted into very lightly doped silicon.
  This allows the doping profile in each well to be
  tailored independently so that neither type of
  device will suffer from excessive doping effects.
  

BiCMOS integrated circuit CMOS finds wide
applications in VLSI circuits due to its
excellent noise margin, low drive current and
vitually zero standby power consumption. However
there are increasing demands to fabricate bipolar
transistors on CMOS chips, particularly for
drivers and high performance analog circuits.
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In principle, the same number of steps in CMOS
fabrication can be used to incorporate the base
and emitter regions of the bipolar transistor.
However it assumes that the emitter and base
regions are compatible with the requirements of
the CMOS source and drain. In reality, for CMOS
which already has a given set of design rules for
source and drain implants, and channel implants
(for controlling the threshold voltage), at least
one additional step is required in order to
incorporate a bipolar transistor on the same
chip.
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9. Design of Integrated Circuits 9.1 Overview of
the IC design process The goal of the IC
designer is to design an integrated circuit that
meets a given set of specification with minimum
labor in the shortest time. The conventional
approach to circuit design often involves much
iteration at the breadboard level. Due to the
complexity in VLSI, powerful computer-aided-design
tools are required to perform schematic capture,
simulation and mask layout in the design
process.
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There can be two philosophical approaches to IC
design i) in the bottom-up approach, the
designer starts at the transistor or gate level
and designs subcircuits of increasing complexity,
which are then interconnected to realize the
required functionality ii) in the top-down
approach, the designer repeatedly decomposes the
system-level specification into groups, and
subgroups of simpler tasks. The lowest-level
tasks are ultimately implemented in silicon,
either with standard circuits or with low-level
circuits designed to meet the required
specification. In the extreme case, the top-down
approach results in a silicon compiler, in which
all blocks are automatically designed with a
computer. The top-down approach is especially
useful in large scale digital circuits which are
regular and repetitive in structure. In practice,
combinations of top-down and bottom-up concepts
are used in varying degrees.
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Block diagram of IC design process
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• 9.2 Custom and semi-custom IC design
• Standard configuration ICs (including
  microprocessors, memories and other logic
  sub-systems)
• ICs designed specifically to meet a particular
  function
• (a) fully custom design - all the circuits and
  mask layouts are completely designed for the
  requirements of a particular IC, used in large
  volume production.
• (b) semi-custom approach using gate arrays or
  standard cells - often used for speedy design
  with less effort compared to custom design.

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Gate arrays are integrated circuits containing
large numbers of digital gates or transistor
cells, which can be interconnected in different
ways to implement various logic functions.
Wafers containing these gate arrays have been
processed up to all steps except the
metallisation layers. Using computer-aided-design
tools, only the metallisaton layer patterns are
required to be generated from the circuit
specification, and the fabrication time can be
very short. Gate arrays can have several
metallisation layers to facilitate
interconnection.
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Standard cell design relies on the extraction of
mask layouts from a set of pre-designed
logic/circuit cells. To facilitate placement and
routing, the standard cells are designed to have
equal height but variable widths, so that the
final IC layout will have a regular pattern with
rows of cells and interconnect routing running
between the rows.
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9.3 Design rule and mask layout Design rule is a
set of regulations which define the acceptable
dimensions and electrical characteristics
achievable in a fabrication process. The IC
designer must observe these rules in the creation
of circuits and mask geometry layout. Design
rules usually consist of three parts
i) geometric rules governing the features,
patterns and relationship between mask layers as
determined by the process technology. ii)
mandatory requirements including alignment marks,
scribe channel definition, bonding pads. iii)
electrical parameters, e.g. transistor gain,
threshold voltage, capacitance values.
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Geometric layout rules are divided into the
following types i) the minimum width of a layer
(e.g. metal, diffusion, poly)
ii) the minimum space in a layer, e.g. the
minimum space that can be reliably etched in
metal, poly layers, or that is electrically
feasible in diffusion layer iii) the minimum
overlap between two layers, e.g. between the
contact and diffusion layers, an overlap is
necessary due to misalignment, enlarging of
contact size and shrinking of diffusion area. iv)
the minimum separation between two different
layers, e.g. due to misalignment, shrinkage or
enlargement of features during etching.
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Mead and Conway (1980) introduced the concept of
? based design rule by normalizing all geometric
design rules by a basic parameter ?, i.e. all
mask pattern dimensions are expressed as
multiples of ?. The unit ? is set by mask
alignment tolerance, overstretching or
under-etching, photoresist tolerance etc. The
advantage of using ? based design rule is that
the mask layout can be simply scaled down
proportionally if the minimum feature of the
fabrication process is reduced.
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10. Digital IC circuit design 10.1 NMOS logic
circuits (a) Basic inverter consists of a
pull-down transistor M1 and a pull-up transistor
M2. M2 can be either a depletion transistor (in
depletion-load inverter) or an enhancement
transistor (in enhancement-load inverter).
Following diags. show the circuit of the
inverters and the transfer characteristics. In
the enhancement load inverter, the output voltage
in the high state is only VDD-VTN, which is less
than that (VDD) in the depletion load inverter.
Therefore the depletion load inverter is
preferred due to the larger output voltage swing
and higher noise immunity.
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Inverter device sizing Consider the
depletion-load inverter. Because the output high
voltage VHVDD, it is desirable to design the
switching voltage at VDD/2. With proper design,
both transistors are saturated, and the output
voltage is equal to VDD/2 when the input is at
VDD/2. Equating the drain currents of M1
M2, where VTN,VTD are the threshold
voltages of the enhancement and depletion
devices. In a typical 5V supply NMOS, VTN is
about 1 V, VTD is about -3V. Solving, we obtain

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(b) NMOS NOR gate circuit
Minimum sizing rule
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(c) NMOS Nand Logic Circuit
Minimum Sizing rule
Series resistance of M1 M2 is equivalent to the
pull-down transistor in the inverter.
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10.2 Complementary MOS Logic circuits CMOS IC
has low power consumption (power is only consumed
during switching of the gates), and high noise
immunity. The CMOS fabrication process is more
complicated than NMOS. It consumes more Si area
as compared with NMOS. The power consumption in
CMOS is proportional to the clock frequency in
digital circuits. CMOS is the present standard
logic family used in VLSI digital ICs.
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a) CMOS inverter
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The CMOS inverter is a ratioless logic circuit,
meaning that the steady state output voltage
levels are independent of the ratio of the pull
up/pull down transistor sizes. The voltage swing
is almost between VDD and zero. The primary
effect of the sizes of the pull-up and pull-down
transistors is on the equivalent resistance of
the transistors in the conducting state.
Thus, sizing can be used to provide approximately
equal capability to source or sink load current.
In contrast, NMOS inverters provide asymmetric
output drive because of the difference in pull-up
and pull-down resistance needed to achieve useful
logic levels. The symmetric drive capability of
CMOS allows comparable transition times for
output voltages irrespective of the direction of
transition.
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The transductacne parameter K'N of an n-channel
transistor is about 2 to 3 times that of the
p-channel transistor K'P. (This is because K is
proportional to majority carrier mobility in the
channel, and electron mobility is higher than
hole mobility.) The equivalent resistance for the
n-channel and p-channel transistors are given
by
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Simple models for the transistors consist of an
ideal switch in series with the equivalent
resistances. The model is useful for predicting
current drive capability and propagation delays.
For symmetric output drive, RNRP, and the device
sizing should be It means p-channel
transistor has a width of 2.5 times that of the
n-channel transistor for equal channel length.
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(b) CMOS NOR gate
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The pull-up resistance is due to the sum of
transistors M3, M4 The pull-down
resistance can be either RN1, RN2 or their
parallel combination depending on the input
conditions. Usually the devices are sized so that
the worst drive capability is as good as that of
the reference inverter. If M1 M2 are of minimum
size, then the pull-up transistors would both
have W/L5 to maintain the worst-case drive
capability.
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(c) CMOS Nand Gate
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For the NAND gate, the series path to ground
uses n-channel transistors, and the parallel path
to VDD uses p-channel transistors. Based on
minimum-size transistors and a 2.51
transconductance advantage of n-channel over
p-channel transistors, the series resistance of
two n-channel transistors to ground is nearly
matched by a single p-channel pull-up to VDD.
This near-symmetry makes the NAND gate the
preferred CMOS logic form.
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10.3 Transmission gates Because a MOS transistor
is an excellent switch, it is possible to connect
the transistor in series with a logic signal so
that the signal is either passed or inhibited.
This structure is called a transmission gate.
NMOS transmission gate
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Multiplexer using transmission gates
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CMOS transmission gate