BTeV Pixel Readout Chip Status

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BTeV Pixel Readout Chip Status

• Gabriele Chiodini - Fermilab
• On behalf of the BTeV pixel group

BTeV Directors Status Review Fermilab, Sept 30
- Oct 2, 2002
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Outline of the talk

• Next BTeV pixel readout chip submission
• FPIX2 chip
• FPIX history
• Irradiation tests of chip prototypes
• Total dose
• Single Event Effects
• Detector assembly
• Conclusions

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FPIX2 October 2002 submission
Test outputs

• FPIX2 submission this month (Oct. 02)
• TSMC (Taiwan Semic. Man. Corp.)
• 0.25um CMOS, 5 metals, 2.5V.
• Rad-Hard layout.
• BTeV Full-sized chip.
• All the functionality required by BTeV.
• Submission based on the successful results of
  smaller-scale chip prototypes.
• One row of 70 pads for wire bonding.
• Internal bond pads for chip Id.

22 cols by 128 rows
Chip periphery
Internal bond pads for Chip ID
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FPIX2 Front-End

• FE optimized for 132 ns BCO.
• DC leakage current compensation.
• 3 Bit Flash ADC/cell.

Analog response of the Charge Sensitive Amplifier
before and after exposure to 33 Mrad(Si) gs from
a Co60 source at Argonne.
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FPIX2 block diagrams

• Kill and charge-injection shift-regs.
• 4 timestamp regs in End of Column.
• High speed data driven column architecture.
• High speed data output serializer
• 1,2,4, or 6 lines
• 140 Mbits-1line-1
• Programmable biases and thresholds by DACs.
• LVDS I/O signals
• point to point for data output
• bussed for control
• Robust absolute addressing used for
  programming I/O.

• All circuit blocks tested. Complete functionality
  at
• Full speed.
• Before and after irradiation.

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FPIX history

• 1997 FPIX0, 12x64 array, HP 0.8 um CMOS
• Two stage front-end, analog output digitized off
  chip, data driven non-triggered Readout.
• Successfully used in beam tests.
• 1998 FPIX1, 18x160 array, HP 0.5 um CMOS
• Two stage front-end, 2 bit FADC/cell.
• Fast triggered/non triggered R/O.
• Successfully used in beam tests.
• 1999 PreFPIX2_T, 2x160 array, TSMC 0.25 um CMOS
• New leakage compensation strategy implemented in
  radiation tolerant techniques.
• 3 bit FADC/cell.
• g irradiation to a total dose of 33 Mrad.
• 2000 PreFPIX2_I, 18x32 array, CERN 0.25 um CMOS
• Complete fast non-triggered RO.
• p irradiation tests to a total dose of 26 Mrad.
• PreFPIX2_Tb 18x32 array, TSMC 0.25 um CMOS
• Programmable 14 x 8 bit DACs.
• p irradiation tests to a total dose of 87 Mrad
  and SEU tests.
• 2002 Data output interface prototype, TSMC 0.25
  um CMOS
• LVDS drivers.

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Total Dose Tolerance

• Threshold shifts g and hadrons.
• Small as expected.
• Surface leakage currents g and hadrons.
• Negligible by design (gate all around NFETs and
  guard rings).
• Bulk damage hadrons.
• Small, manageable, increase in leakage due to
  parasitic device formation.
• High statistics with 200 MeV protons exposure
• Four chips exposed up to 26 Mrad.
• Two chips exposed up to 14 Mrad.
• Two chips exposed up to 29 Mrad.
• One chip exposed up to 14, 43, and 87 Mrad.
• All cells worked before and after exposure
  (screened up to 4032 Front-End cells)

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200 MeV p
200 MeV p
Noise distribution among cells from most
irradiated chip.
200 MeV p
Threshold distribution among cells from most
irradiated chip.
Qover-drive150e- TW 130 ns
Time walk performance very good before and after
irradiation.
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Deviation from the linearity of the first
threshold DAC vs total dose.
Linear fit of the DAC response before irradiation
200 MeV p
Deviation of DAC response for various doses with
respect to the linear fit done before irradiation

• Non-lin. before irr. about 0.2
• Non-lin. after 87 Mrad about 3

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Single Event Effect Tolerance

• Catastrophic events gate rupture, latch up.
• None observed ? rate guaranteed to be acceptable
  to BTeV.
• Soft errors Single Event Upset (SEU).
• Small cross sections per bit measured
• From 1 to 6x10-16 cm2bit-1 for static registers.
• About 2x10-15cm2bit-1 for 140 MHz clocked
  registers.

Expected SEU error in one hour in full pixel
vertex detector at the nominal luminosity of
L2x1032cm-2s-1. ? no need for redundant logic or
other design measures.
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Experimental SEU error tables
Static registers

• Most chips facing the beam.
• Two chips at 450 and 1800.
• One chip indium bump bonded to sensor array.
• All data statistically consistent.

transition from 0 to 1 transition from 1 to
0
Data Output Serializer

• Test done at nominal speed of 140 Mbit/s
  line.
• No word errors for 12 hours after a dose of 29
  Mrad with beam off.

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LVDS drivers
Scope
LVDS to CMOS
Clock
Pattern Generator
LVDS driver
Single ended random pattern
LVDS signals drive 50 feet flat-end-twisted cable

• FPIX readout chips are the only active device on
  the module.
• 30 foot Copper point-to-point links will connect
  the FPIX chips to FPGAs located behind the
  magnet.

Reference clock 70 MHz
140Mbit/s 64kbit random pattern output after 50
foot
140Mbit/s eye-pattern of on-chip LVDS drivers
after 50 foot flat-and-twisted cable.
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Rad-hard detector assembly
Xray sources e- Tb, Ag, Rb
Pulser relative calibration V
CiS-moderated-pspray
preFPIX2Tb
Threshold dispersion 340 e- Average noise 110
e-
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Conclusions

• The building blocks of the current design have
  all been tested successfully in smaller-scale
  chips.
• Now, it is time to put all the elements together
  and submit a full-sized pixel readout chip
  designed to meet all BTeV requirements.
• The full-sized chip will allow us to
• Test multi-chip modules appropriate for the BTeV
  vertex detector layout.
• Assemble and test a relatively large number of
  bump bonded assemblies.
• Understand bump bonding assembly yield
• Validate multiple vendors
• Conduct tests with increasingly large pixel
  systems, leading up to a 10 test.
• Ready for production.