Arithmetic Circuits

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Arithmetic Circuits

• Anselmo Lastra

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Administrative

• May have messed up scoring of HW1
• Because I went for 100 total and didnt use the
  25 point scale on web page
• Look at yours and send it back if I made mistake.

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Iterative Circuit

• Like a hierachy, except functional blocks per bit

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Adders

• Great example of this type of design
• Design 1-bit circuit, then expand
• Look at
• Half adder 2-bit adder, no carry in
• Inputs are bits to be added
• Outputs result and possible carry
• Full adder includes carry in, really a 3-bit
  adder

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Half Adder

• S X ? Y
• C XY

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Full Adder

• Three inputs. Third is Cin
• Two outputs sum and carry

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K Map for S

• What is this?

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K Map for C
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Two Half Adders (and an OR)
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Ripple-Carry Adder

• Straightforward connect full adders
• Carry-out to carry-in chain
• C0 in case this is part of larger chain, maybe
  just set to zero

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Hierarchical 4-Bit Adder

• We can easily use hierarchy here
• Design half adder
• Use in full adder
• Use full adder in 4-bit adder
• Verilog code from textbook
• First part of lab

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Verilog Half Adder

• module half_adder_v(x, y, s, c)
• input x, y
• output s, c
• assign s x y
• assign c x y
• endmodule

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Verilog Full Adder

• module full_adder_v(x, y, z, s, c)
• input x, y, z
• output s, c
• half_adder_v HA1(x, y, hs, hc),
• HA2(hs, z, s, tc)
• assign c tc hc
• endmodule

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Four-Bit Adder

• module adder_4_v(B, A, C0, S, C4)
• input30 B, A
• input C0
• output30 S
• output C4
• wire31 C
• full_adder_v Bit0(B0, A0, C0, S0, C1),
• Bit1(B1, A1, C1, S1,
  C2),
• Bit2(B2, A2, C2, S2,
  C3),
• Bit3(B3, A3, C3, S3, C4)
• endmodule

Look at connections between adders
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Behavioral Verilog

• // 4-bit Adder Behavioral Verilog
• module adder_4_b_v(A, B, C0, S, C4)
• input30 A, B
• input C0
• output30 S
• output C4
• assign C4, S A B C0
• endmodule

Addition (unsigned)
Concatenation operation
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Whats Problem with Design?

• Delay
• Approx how much?
• Imagine a 64-bit adder
• Look at carry chain

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Post Map Delay
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Post Place and Route

• Odd delays caused by placement

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Carry Lookahead Adder

• Note that add itself just 2 level
• Idea is to separate carry from adder function
• Then make carry approx 2-level all way across
  larger adder

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Four-bit Ripple Carry
Reference
Adder function separated from carry
Notice adder has A, B, C in and S out, as well as
G,P out.
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Propagate

• The P signal is called propagate
• P A ? B
• Means to propagate incoming carry

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What Does This Mean?

• No Carry Here
• So the propagate signal indicates that condition
  of incoming should pass on

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Generate

• The G is generate
• Its G AB, so new carry created
• So its ORed with incoming carry

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Said Differently

• If A ? B and theres incoming carry, carry will
  be propagated
• And S will be 0, of course
• If AB, then will create carry
• Incoming will determine whether S is 0 or 1

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Ripple Carry Delay 8 Gates
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Turn Into Two Gate Delays

• Design changed from deep (in delay) to wide

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C1 Just Like Ripple Carry
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C2 Circuit Two Levels
G from before and P to pass on
This checks two propagates and a carry in
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C3 Circuit Two Levels
Generate from level 0 and two propagates
G from before and P to pass on
This checks three propagates and a carry in
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What Happens as Scale Up?

• Can I realistically make 64-bit adder like this?
• Have to AND 63 propagates and Cin!
• Compromise
• Hierarchical design
• More levels of gates

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Making 4-Bit Adder Module

• Create propagate and generate signals for whole
  module

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Group Propagate

• Make propagate of whole 4-bit block
• P0-3 P3P2P1P0

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Group Generate

• Does G created upstream pass on because of string
  of Ps (also G3)?
• Indicates carry generated in block

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Hierarchical Carry
A
B
4-bit adder
S
G
P
Cin
C4
C8
Look Ahead
C0

• Left lookahead block is exercise for you

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Practical Matters

• FPGAs like ours have limited fan-in
• Instead they have special circuits to make adders
• So dont expect to see same results as theory
  would suggest

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Binary Subtraction

• Use unsigned subtraction to motivate use of
  complemented representation
• Imagine a subtractor circuit (next)

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One-bit Subtractor

• Inputs Borrow in, minuend and subtrahend
• Review subtrahend is subtracted from minuend
• Outputs Difference, borrow out
• Lets make truth table
• See how it expands
• Next slide

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Example
If no borrow, then result is non-negative
(minuend gt subtrahend).
Since there is borrow, result must be
negative. The result must be corrected to a
negative number. Next slide.
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Correcting Result

• What, mathematically, does it mean to borrow?
• If borrowing at digit i-1 you are adding 2i
• Next Slide

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Correcting Result 2

• If M is minuend and N subtrahend of numbers
  length n, difference was
• 2n M N
• What we want is magnitude of N-M with minus sign
  in front
• Can get by subtracting previous result from 2n
• N - M 2n (M N 2n)

This is called 2s complement
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Put Another Way

• This is numerically equivalent to how we do
  subtraction in our heads
• Decide which is greater
• Swap if necessary
• Subtract
• Could build a circuit this way, but expensive

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Algorithm

• Subtract N from M
• If no borrow, then M ? N and result is OK
• Otherwise, N gt M so result must be subtracted
  from 2n and minus sign prepended

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Pretty Expensive Hardware!
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Designs Arent Like This

• Thats why people use complemented interpretation
  for signed numbers
• 2s complement
• 1s complement

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1s Complement

• Given binary number N with n digits
• 1s complement defined as
• (2n 1) - N
• Note that (2n 1) is number with n digits, all
  of them 1
• For n 4, (2n 1) 1111

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Example

• Notice that 1s complement is complement of each
  bit

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2s Complement

• Given binary number N with n digits
• 2s complement defined as
• 2n N for N ? 0
• 0 for N 0
• Exception is so result will always have n bits
• 2s complement is just a 1 added to 1s complement

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Important Property

• Complement of a complement generates original
  number
• NOTE We havent talked about negative numbers
  yet. Still looking at unsigned
• Lets look at new design for subtractor

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New Algorithm for M-N

• Add 2s complement of N to M
• This is M (2n N) M N 2n
• If M ? N, will generate carry (why?)
• Discard carry
• Result is positive M - N
• If M lt N, no end carry (why?)
• Take 2s complement of result
• Place minus sign in front

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Example

• X 101_0100 minus Y 100_0011

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Example 2

• Y 100_0011 minus X 101_0100
• No end carry
• Answer - (2s complement of Sum)
• - 0010001

We said numbers are unsigned. What does this
mean?
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Adder-Subtractor

• Need only adder and complementer for input to
  subtract
• Need selective complementer to make negative
  output back from 2s complement
• Or go through adder again. See next slide

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Design
S low for add, high for subtract
Inverts each bit of B if S is 1
Adds 1 to make 2s complement

• Output is 2s complement if B gt A

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Signed Binary

• First review signed representations
• Signed magnitude
• Left bit is sign, 0 positive, 1 negative
• Other bits are number
• 2s complement
• 1s complement

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Example in 8-bit byte

• Represent -9 in different ways
• Signed magnitude 10001001
• 1s Complement 11110110
• 2s Complement 11110111

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Observations

• 1s C and Signed Mag have two zeros
• 2s C has more negative than positive
• All negative numbers have 1 in high-order

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Advantages/Disadvantages

• Signed magnitude has problem that we need to
  correct after subtraction
• Ones complement has a positive and negative zero
• Twos complement is most popular
• Arithmetic operations easy

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Twos Complement

• Addition easy on any combination of positive and
  negative numbers
• To subtract
• Take 2s complement of subtrahend
• Add
• This performs A ( -B), same as A B

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Examples from Book

• Addition
• 6 13
• -6 13
• 6 (- 13)
• (-6) (-13)
• Subtraction
• -6 - (-13)
• 6 - (- 13)
• Try some of these

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Overflow

• Two cases of overflow for addition of signed
  numbers
• Two large positive numbers overflow into sign bit
• Not enough room for result
• Two large negative numbers added
• Same not enough bits
• Carry out can be OK

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Examples

• 4-bit signed numbers
• 7 7
• 7 7
• Generates carry but result OK
• -7 -7
• 4 4
• Generates no Cout, but overflowed

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Overflow Detection

• Condition is that either Cn-1 or Cn is high, but
  not both

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Multiplier

• Multiply by doing single-bit multiplies and
  shifts
• Look at combinational circuit to do this

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Combinational Multiplier
AND computes A0 B0
Half adder computes sum. Will need FA for larger
multiplier.
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Larger Multiplier
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Sequential Multiply

• Imagine doing over time rather than in parallel
• Bitwise multiply
• Shift
• Add
• If we have time later in semester well look at
  fancier multipliers

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Simple Testbench (Friday lab)

• initial
• begin
• A 4'd0 B 4'd0 C0 1'b0
• 50 A 4'd3 B 4'd4
• 50 A 4'd2 B 4'd5
• 50 A 4'd9 B 4'd9
• 50 A 4'd10 B 4'd15
• 50 A 4'd10 B 4'd5 C0 1'b1
• 50 A 4'd0 B 4'd0 C0 1'b0
• 50 A 4'b1111 B 4'b1111 C0 1'b1
• end

This is impractical, except for initial test.
Use do loop.
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Lab

• Write your lookahead adder in Verilog before lab
• Give you more time to debug any errors
• Suggest you spend some time experimenting with
  testbenches
• Write some programs to test your designs
  different ways

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Homework

• Homework 2 is posted
• Due next Thursday

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Today

• Adders
• Ripple carry
• Carry lookahead
• Subtracting unsigned numbers
• New design for adder-subtractor
• Signed numbers
• Signed addition/subtraction
• Multiplication

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Next

• Sequential Circuits
• Latches
• Flip-Flops
• Start reading Chapter 6