CEG3470

1
CEG3470
Digital Circuits (Spring 2009)
Lecture 4 Switch Logic Inverter Chain
Optimization
Courtesy slides from DIC 2/e and EE141 notes
from Prof. Jan Rabaey

• Tang Wai Chung, Matthew

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CMOS Inverter
Abstract view schematic
Physical view layout
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Two Inverters
Share power and ground
Connect in Metal
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Outline

• Switch model of CMOS transistor
• CMOS inverter static and transient analysis
• Inverter chain optimization
• With fixed number of stages
• optimal number of stages
• buffer design for performance

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What is a Transistor?
An MOS Transistor
A Switch
G
VGSgtVT
VGS
S
D
D
S
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Switch Model of MOS Transistor
G
VGS
D
S
Ron
S
D
S
D
VGSltVT
VGSgtVT
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A Modern Sub-100 nm Look
G
VGS
D
S
Roff
Ron
S
D
S
D
VGSltVT
VGSgtVT
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NMOS and PMOS
G
G
VGSgt0
VGSlt0
D
D
S
S
X
Ron
Y
Z
Y Z if X 1
Y Z if X 0
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The CMOS Inverter A First Glance
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CMOS Inverter First-Order DC Analysis
VDD
VDD
Rp
VOL 0 VOH VDD VM f(Rn, Rp)
V
out
V
out
Rn
Vin 0
Vin VDD
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Simulated VTC
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CMOS Inverter DC Properties

• VOH VDD 2.5V
• VOL 0V
• VM 1.2V
• VIL 1.05V
• VIH 1.45V
• NMH 1.05V
• NML 1.05V

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CMOS Inverter Transient Response
VDD
VDD
Rp
Vout
Vout
CL
CL
Rn
Vin VDD
Vin 0
(a) Low-to-high
(b) High-to-low
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CMOS Properties

• Full rail-to-rail swing
• Symmetrical VTC
• Propagation delay function of load capacitance
  and resistance of transistors
• No static power dissipation
• Direct path current during switching

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Discussions

• Impact of CMOS in
• Reliability
• Performance/Speed
• Power/energy

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Inverter Chain
out
in
CL

• For some given CL
• How many stages are needed to minimize delay?
• How to size the inverters
• Anyone want to guess the solution?

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Careful about Optimization Problems

• Get fastest delay if build one VERY big inverter
• So big that delay is set only by self-loading
• Likely not the problem youre interested in
• Why?

Cload
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Engineering Optimization Problems in General

• Need to have a set of constraints
• Constraints key to
• Making the result useful
• Making the problem have a clean solution
• For sizing problem
• Need to constrain size of first inverter

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Delay Optimization Problem 1

• You are given
• A fixed number of inverters
• The size of the first inverter
• The size of the load that needs to be driven
• Your goal
• Minimize the delay of the inverter chain
• Need model for inverter delay vs. size

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Transistor Resistance and Capacitance
always use H min. height for all transistors to
minimize the channel length
intrinsic delay is proportional Cint SCiref
sizing factor S
H
H
(S)W
W
minimum size transistorwith base unit H
Wdefine resistance Rrefintrinsic cap. Ciref
Wider channels ? Resistance of transistor
reduced by 2R Rref/S
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Inverter Delay

• Assume we want equal rise/fall delays tpHL
  tpLH
• Need approx. equal resistances RN RP
• PMOS has approx. 2 times larger resistance for
  the same size
• Make PMOS 2 times wider WP 2WN 2W
• tp 0.69(Rref/S)CL

Smallest inverter with S 1, then tp0
0.69RrefCiref
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Inverter Delay Model
CL
2W
The loading can be divided into (1) intrinstic
and (2) extrinsic components
Cint
Cext
W

• CL Cint Cext , Cint SCiref
• tp 0.69 (Rref/S)(Cint Cext)
• tp 0.69 (Rref/S)(SCiref)(1 Cext/SCiref)
• tp tp0(1 Cext/SCiref)

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Relating gate cap. with diffusion cap.
Cint/Cg ? constant independent of size
f effective fan-out f Cext/Cg
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Apply to Inverter Chain
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Optimal Tapering for Given N

• Delay equation has (N 1) unknowns, Cin,2
  Cin,N
• To minimize the delay, find (N 1) partial
  derivatives

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Optimal Tapering for Given N (cont)

• Result every stage has equal fanout
• In other words, size of each stage is geometric
  mean of two neighbours
• Equal fanout ? every stage will have same delay.

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Optimum Delay and Number of Stages

• When each stage has same effective fanout f
• Minimum path delay

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Example
CL/C1 has to be evenly distributed across N 3
stages
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Delay Optimization Problem 2

• You are given
• The size of the first inverter
• The size of the load that needs to be driven
• Your goal
• Minimize delay by find optimal number and sizes
  of gates.
• So, need to find N that minimizes

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Solving the Optimization

• Rewrite N in terms of fanout/stage f

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Optimum Effective Fanout f

• Optimum f for given process defined by ?

Optimal f
fopt 3.6
?
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Normalized Delay (tp/tpopt)
Normalized delay
its fine to choose greater then fopt
fopt
sizing factor f
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Normalized Delay as a function of F
? 1
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Buffer Design
N f tp 1 64 65 2 8 18 3 4 15 4 2.8
15.3
1
64
1
8
64
1
4
64
16
1
64
22.6
8
2.8
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Inverter Chain Answers
out
in
CL

• For some given CL
• How many stages are needed to minimize
  delay?Ans N (ln CL/Cin)/ln fopt
• How to size the invertersAns fopt 3.64 for ?
  1 in most CMOS