CEG3470

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CEG3470
Digital Circuits (Spring 2009)
Lecture 5 Designing Combinational Logic Circuits
Courtesy slides from DIC 2/e and EE141 notes
from Prof. Jan Rabaey

• Tang Wai Chung, Matthew

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Combinational vs. Sequential Logic
Out
In
Combinational
Combinational
Out
In
Logic
Logic
Circuit
Circuit
State
Combinational
Sequential
Output f(input)
Output f(input, state)
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Static CMOS Circuit

• At every point in time (except during the
  switching transients) each gate output is
  connected to either VDD or VSS(GND) via a low
  resistive path.
• The outputs of the gates assume at all times the
  value of the Boolean function implemented by the
  circuit (ignoring the transient effects during
  switching periods)

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Static Complementary CMOS
VDD
in1
PMOS only
in2
PUN

inN
F(In1,In2,InN)
in1
NMOS only
in2
PDN

inN
PUN and PDN are dual logic networks
PUN and PDN functions are complementary.
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
Y X if A AND B
AND
OR
Y X if A OR B
NMOS Transistors pass a strong 0 but a weak 1
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PMOS Transistors in Series/Parallel Connection
PMOS switch closes when switch control input is
low
A
B
NOR
Y X if A AND B' (A B)
X
Y
A
NAND
B
Y X if A OR B (AB)
X
Y
NMOS Transistors pass a strong 1 but a weak 0
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Threshold Drops
VDD
VDD
PUN
S
D
VDD
0 ? VDD - VTn
D
S
0 ? VDD
VGS
CL
CL
VDD ? VTp
VDD ? 0
PDN
VGS
S
D
CL
CL
VDD
D
S
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Complementary CMOS Logic Style

• PUN is the dual to PDN(can be shown using
  DeMorgans Theorems)
• Static CMOS gates are always inverting.

AND NAND INV
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Example Gate NAND
VDD
B
A
A
Truth table of a 2-input NAND gate
B

• PDN G AB ? Conduction to GND
• PUN F A B (AB) ? Conduction to VDD
• In general, G(in1, in2, in3, ...) F(in1, in2,
  in3, ...)

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Example Gate NOR
Truth table of a 2-input NOR gate
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Complex CMOS Gate
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Optimizing Combinational Logic Logical Effort
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Question 1

• All of these are decoders
• Which one is best?

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Question 2

• Is it better to drive a big capacitive load
  directly with the NAND gate, of after some
  buffering?

CL
CL
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Recap Buffer Sizing
For given N Ci1/Ci Ci/Ci-1 To find N Ci1/Ci
4 How to generalize this to any logic path?
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Delay of NAND Gate
Cinand 6CD 2Ciref Cgnand 4CG
(4/3)Cginv Ciref/Cginv ? Ciref ?Cginv (3/4)
?Cgnand
VDD
A
B
2
2
A
2
tpnand 0.69 R(Cint Cext) 0.69
(Rref/1)(2Ciref Cext) 0.69 (RrefCiref)(2
Cext/Ciref) tp0 (2 (4/3)Cext/?Cgnand) tp0
(2 (4/3)f/?)
2
B
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Delay of NOR Gate

• How you size the transistors so that the
  resistance is equivalent to an inverter?
• Express diff. cap. and gate cap. of the NOR gate
  in terms of that of a standard size inverter.
• Calculate the delay in terms of tp0

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Logical Effort
p intrinsic delay - gate parameter ? f(W) g
logical effort gate parameter ? f(W) f
effective fanout Normalize everything to an
inverter ginv 1, pinv 1 Divide everything
by tp0 (everything is measured in unit delays
tp0) Assume g 1.
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Delay in a Logic Gate
Logical effort is a function of topology,
independent of sizing Effective fanout
(electrical effort) is a function of load/gate
size
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Logical Effort

• Inverter has the smallest logical effort and
  intrinsic delay of all static CMOS gates
• Logical effort of a gate presents the ratio of
  its input capacitance to the inverter capacitance
  when sized to deliver the same current
• Logical effort increases with the gate complexity

g (Req,gateCin,gate)/(Req,invCin,inv)
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Logical Effort
Calculate LE by sizing for same drive strength
g 1
g 4/3
g 5/3
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Logical Effort of Gates
g 4/3 p 2 d 2 (4/3)f/?
tpNAND
g 1 p 1 d 1 f/?
tpINV
Normalized delay (d)

effort delay
p Fan-in
intrinsic delay
1
2
3
4
5
6
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Fan-out (f/?)
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Intrinsic Delay for Common Gates
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Logical Efforts for Common Gates
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Gate Sizing Convention

• Need to set a convention
• What does a gate of size 2 mean?
• For an inverter it is clear
• Cinv 2, Rinv 1/2
• For a gate, two possibilities
• Cgate 2Cinv
• Rgate Rinv / 2
• In the notes, size Cgate/Cinv
• Size 2 gate has twice input capacitance of a unit
  inverter.

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Multistage Networks
Effective effort hi fi gi Path electrical
effort F Cout/Cin Path logical effort G
g1g2gN ? gi Branching effort B b1b2bN
?bi Path effort H ?hi GF Path delay D ?di
? pi ?hi
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Optimum Effort per Stage
When each stage bears the same effort
Effective efforts g1f1 g2f2 gNfN
Effective fanout of each stage
Minimum path delay
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Optimal Number of Stages
For a given load, and given input capacitance of
the first gate Find optimal number of stages and
optimal sizing
Remember we can always add inverters to the end
of the chain
Substitute best stage effort h H1/N is still
around 4.
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Example Optimize Path
g 1f a
g 1f 5/c
g 5/3f b/a
g 5/3f c/b
Effective fanout, F G H h a b
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Example Optimize Path
g 1f a
g 1f 5/c
g 5/3f b/a
g 5/3f c/b
Effective fanout, F 5 G 1 x 5/3 x 5/3 x 1
25/9 H G x F 125/9 h (125/9)1/4 1.93 a
1.93 b 2.23 c 2.59
5/c 1.93 (5/3)(c/b) 1.93 (5/3)(b/a) 1.93
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Example 8-input AND
g 10/3 1 G 10/3 P 8 1
g 2 5/3 G 10/3 P 4 2
g 4/3 5/3 4/3 1 G 80/27 P 2 2
2 1
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Multistage Networks
Effective effort hi fi gi Path electrical
effort F Cout/Cin Path logical effort G
g1g2gN ? gi Branching effort B b1b2bN
?bi Path effort H ?hi ?bi GFB Path delay D
?di ? pi ?hi
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Add Branching Effort
Branching effort
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Branching Example 1
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g 1 F 90/5 H 18 (wrong!)
5
90
h1 (15 15)/5 6 h2 90/15 6 H 36
15
90
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Branching Example 2
Select gate sizes y and z to minimize delay from
A to B
G (4/3)3 F Cout/Cin 9 B 2 x 3 6 H GFB
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Best h (H)1/3 5 d tp0(2 5) x 3
21tp0 Working backward for sizes z 9C x
(4/3)/5 2.4C y 3z x (4/3)/5 1.9C
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Determine Final Sizing

• With this convention, we can relate sizing with
  the fanout, logical effort and branching factor

• Finally a general formula with find all sizes
  from the first gate

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Method of Logical Effort

• Compute the path effort H GFB
• Find the best number of stages N log4F
• Compute the stage effort h H1/N
• Sketch the path with this number of stages
• Work either from either end, find fanouts f
  g/h
• Finally sizes

Reference Sutherland, Sproull, Harris, Logical
Effort, Morgan-Kaufmann 1999.
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Summary
Sutherland, Sproull, Harris