CEG3470

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CEG3470
Digital Circuits (Spring 2009)
Lecture 11 Fast Complex Gates and Ratioed Logic
Courtesy slides from DIC 2/e and EE141 notes
from Prof. Jan Rabaey

• Tang Wai Chung, Matthew

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Analyzing and Optimizing Complex CMOS Gates

• Techniques very similar to the inverter case
• Logical effort techniques as the means for gate
  sizing and topology optimization
• This guides us to design logic gates with similar
  driving strength as an inverter.
• However, we still have to aware of RC network
  propagation delay ? fan-in restriction

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Fan-in Considerations
RC Model
A
B
C
D
2
2
2
2
A
CL
4
C3
B
4
C2
C
4
C1
D0?1
4
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Fan-in Considerations (2)
RC Model
tpHL 0.69 Reqn(C1 2C2 3C3 4CL)
Propagation delay deteriorates rapidly as a
function of fan-in quadratically in the worst
case.
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tp as a Function of Fan-in
quadratic
tp (ns)
linear
fan-in
Gates with a fan-in greater than 4 should be
avoided.
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tp as a Function of Fan-out
tp (ns)
fan-out
All gates have the same drive current. Slope is a
function of driving strength.
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tp as a Function of Fan-in and Fan-out

• Fan-in quadratic due to increasing resistance
  and capacitance
• Fan-out each additional fan-out gate adds two
  gate capacitances to CL

Empirical Formula
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Fast Gates Design Technique 1

• Transistor sizing
• As long as fan-out capacitance dominates
• Progressive sizing
• M1 gt M2 gt M3 gt ... gt MN(the FET closest to the
  output is the smallest)
• Can reduce delay by more than 20
• Be carefulinput loading junction caps

inN
MN
CL
in3
C3
M3
in2
M2
C2
in1
C1
M1
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Fast Gates Design Technique 2

• Transistor ordering

critical path
critical path
charged
charged
1
0?1
CL
CL
in3
in3
M3
M3
1
1
charged
discharged
in2
in2
M2
M2
C2
C2
0?1
1
charged
discharged
in1
in1
C1
C1
M1
M1
delay determined by time to discharge CL, C1 and
C2
delay determined by time to discharge CL
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Fast Gates Design Technique 3

• Alternative logic structures

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Fast Gates Design Technique 4

• Isolating fan-in from fan-out using buffer
  insertion

CL
CL
Always remember that inverter is a best gate to
drive signals.
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Ratioed Logic
Resistive-load Inverter
Pseudo-NMOS Inverter

• Goal build gates faster/smaller than static
  complementary CMOS

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Ratioed Logic

• Spend power for speed
• What is the best gate topology for this? (NAND
  vs NOR)
• DC characteristics of Ratioed Logic
• VOH VDD
• VOL depends on PMOS or NMOS ratio
• Ratioed logic is still static since you can
  always find a low-resistive to supplies.

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Pseudo-NMOS VTC
To get low VOL, you need to make the PMOS as
small as possible.
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Ratioed Logic L.E.

• Rising and falling delays are not the same
• Calculate L.E. for the two edges separately

W
W
W
W

• For tpLH
• Cgate WCG Cinv 3WCG
• gLH (2RinvWCG)/(Rinvx3WCG) 2/3

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Ratioed Logic L.E. (pull-down edge)
RP
W
W
W
W
CL
RN
Switch Model

• What is the L.E. for tpHL?
• Switch model would predict Reff RN RL
• Would this give the right answer?

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Response on Falling Edge

• Time constant is smaller, but it takes more time
  to complete 50 VDD transient
• RP actually takes some current away from
  discharging CL.

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Deriving the Time Constant
RP
RN
CL
static
dynamic
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Ratioed Logic Pull-down Delay

• Think in terms of the current driving C_load
• When you have a conflict between currents
• Available current is the difference between the
  two
• In pseudo-NMOS case
• works because RP gtgt RN for good noise margin

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Ratioed Logic L.E. (Pull-down Edge)
W
W
W
W

• For tpHL (assuming RP 2RN)
• Rgate RN/(1 - RN/RP) 2RN Rinv RN
• Cgate WCG Cinv 3WCG
• gLH (2RN x WCG)/(RN x 3WCG) 2/3
• L.E. is lower than an inverter!
• Drawbacks significant static power dissipation

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Adaptive Loads

• control the resistance of the load with the
  enable signal.
• When you pull up, turn of M1 ? small resistance
• When you pull down, turn on M1 ? large resistance
  ? low VOL

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Differential Cascode Voltage Switch Logic (DCVSL)

• PDN1 and PDN2 are complementary.
• When PDN1 pulls down (out 0), PDN2 is cut-off ?
  M2 is turned on to pull up out
• or vice versa

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DCVSL XOR-XNOR Gate
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DCVL Transient Response