Shekhar Borkar

1
Session 6

• Shekhar Borkar
• 6.1 Design and Reliability Challenges in
  Nanometer Technology

Thank you for silencing all cell phones and
pagers and participating in the DAC Attendee
Survey at the end of the Session
2
Design and Reliability Challenges in Nanometer
Technologies

• Shekhar Borkar, Tanay Karnik, Vivek De
• Circuit Research, Intel Labs

3
Outline

• Static variations
• Dynamic variations
• Circuit, microarchitecture, and methodology
• Extreme variations
• Long term challenge
• Summary

4
Static Variations

• Process variations
• Within-die
• Die-to-die
• Static for each die

5
Random Dopant Fluctuations
Causes Vt Variations
6
Sub-wavelength Lithography
Lithography Wavelength
365nm
248nm
193nm
180nm
130nm
Gap
90nm
65nm
Generation
45nm
32nm
13nm EUV
7
Impact of Static Variations
1.4
Frequency 30 Leakage Power 5-10X
30
1.3
1.2
130nm 1000 samples
Normalized Frequency
1.1
1.0
5X
0.9
1
2
3
4
5
Normalized Leakage (Isb)
8
WID-Variation Scaling
Variation components
CD control
If CD control fixed of nominal gate length
Random variations more dominant with scaling
9
Impact on Microarchitecture
Deeper pipelining worsens random variation
impact Total variation impact insensitive to
pipeline depth Variations worsen with increasing
critical paths
10
Dynamic Variations

• Voltage
• Activity change
• Power deliveryRLC
• Dynamicns to 10-100 uSec
• Within die
• Temperature
• Change in activity and ambient
• Dynamic 100s of uSec to mSec
• Within die

11
Voltage Temperature
Temperature Variation (C) Hot spots
Heat Flux (W/cm2) Results in Vcc variation
12
Adaptive Body Bias--Experiment
Multiple subsites
Resistor Network
5.3 mm
4.5 mm
1.6 X 0.24 mm, 21 sites per die 150nm CMOS
Technology
150nm CMOS
Number of
21
Die frequency Min(F1..F21) Die power
Sum(P1..P21)
subsites per die
0.5V FBB to
Body bias range
0.5V RBB
Bias resolution
32 mV
13
Adaptive Body Bias--Results
100
60
Accepted die
20
0
Higher Frequency ?
14
Adaptive supply voltage
15
Adaptive Supply Body Bias
Adaptive supply
Adaptive body bias
Adaptive body bias
Adaptive supply body bias
16
Limitations of Deterministic Design
Transistor sizing
Multi-Vt
multi-Vt
10X
single-Vt
17
Probabilistic Design Concept
WID temperature profileNode activity data
WID CD variationsWID drive current profileWID
leakage current profile
actual
Systematic variations
estimated
Post-silicon tuning
Best pre-silicon design
Size transistorsAssign Vt
Maximize metric
FINAL DESIGN
Probabilistic optimization metric
18
Extreme Variations

• Soft errors
• Electromigration
• Time dependent device degradation

19
SER Strike on Si Device
neutron strike
Thin TOX
p
1
0
Deep s/d
p


- - - -
-


-
Halo/pocket
Retrograde Well
-
-
n-well
STI
Transistor Device
Strikes release electron hole pairs Absorbed
by source drain to alter the state
20
Measurements at LANL
21
SRAM SER Scaling Projections
measured
0.18µm
0.25µm
65nm
90nm
0.13µm
8 increase in SER/bit per generation
22
Standard Latch Sensitivity
L to H
H to L
N1
N0
T5
T7
CK
CK
T8
D
CK

• Strike on N0 propagates to N1
• Stored bit value becomes reversed

23
SEU Tolerant Latch Design
24
Standard vs Tolerant Keeper

• Tolerant keeper devices sized half of standard
  sizes for same performance
• Only 2 stable states out of 16 HLHL, LHLH

25
Measured SER at LANSCE
30x
100x

• SER tolerant latches show 30-100x reduction

26
Long Term Challenge

• Derived from the Gelsinger Guiding Observations
• Transistors are free
• Power is the only real limiter
• Optimizing area freq achieves neither
• 10-100B transistors available, but
• Any 10 beyond 6 sigma (variations)
• Must fit within the power envelope
• Error tolerant (SER, electromigration,)
• Still delivers desired performance
• Robust resilient circuits mArch

27
Resiliency Multieverywhere
Logic Block Level
Full Chip Level

• Multi-core, each core Multi-threaded
• Shared cache and front side bus
• Each core has different Vdd Freq
• Core hopping to spread hot spots
• Lower junction temperature

28
Summary

• Parameter variations will become worse with
  technology scaling
• Major shift from deterministic to probabilistic
  design
• Multi-variable design optimizations considering
  parameter variations
• Robust variation tolerant circuits and
  microarchitectures