Diapositiva 1

1
Unit
Input BW
Output BW
Latency
Streamer
1 index
1 vertex
Mem
Primitive Assembly
1 vertex
1 triang.
1
Clipping
1 triang.
1 triang.
6
Triangle Setup
1 triang.
1 triang.
10
Fragment Generation
1 triang.
2x64 frag.
1
Hierarchical Z
2x64 frag.
2x64 frag.
1
Z Tests
4 frag.
4 frag.
2Mem
Interpolator
2x4 frag.
2x4 frag.
2 to 8
Color Write
4 frag.
2Mem
Unified Shader (vertex)
1 vertex
1 vertex
variable
Unified Shader (fragment)
4 frag.
4 frag.
variable
Table 1. Inputs, outputs and latencies in the
reference ATTILA architecture