Dr Richard Reilly

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Lecture 9

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• Dr Richard Reilly
• Dept. of Electronic Electrical Engineering
• Room 153,
• Engineering Building

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General Purpose Architecture
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Harvard Architecture

• Faster implementation of algorithms
• Gives near real-time performance.

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Intel launches new Processors

• Intel Corp. (Monday 9th Feb) launched four
  microprocessors for desktop applications.
• Code-named Prescott, the slowest microprocessor
  runs at 2.8 GHz, it has
• 1-MB of cache
• 800-MHz front-side bus
• Sells for 178.
• The other three, which have the same FSB and
  cache, have clock speeds of 3, 3.2 and 3.4 GHz,
  and sell for 218, 278, and 417, respectively.

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Intel launches new Processors

• The processors, built with Intel's new
  high-volume 90-nanometer manufacturing
  technology, are aimed directly at Advanced Micro
  Devices Inc. (AMD)
• Analysts say AMD is struggling to keep pace with
  Intel in the processor and process technology
  race.
• Intel is also preparing to reduce prices on its
  current Pentium 4-based chips by up to 33.
• Intel is producing 64-bit processor in a move to
  better compete against AMD's own 64-bit chip
  products.

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Sony and Toshiba expand cooperation

• On Thursday 12th February, Sony and Toshiba
  agreed to expand their cooperation to develop
  technology for new microprocessors.
• Companies will pool resources on development of
  technology for microprocessors whose smallest
  features measure 45nm.
• Both will invest 94.3 million in the project
  scheduled to run until 2005.
• If development succeeds, their microprocessors
  will be significantly smaller, faster and consume
  less power than today's cutting-edge
  microprocessors(which have features as small as
  90nm).
• Such microprocessors are expected to be
  foundation for more advanced devices and will be
  the "Cell" microprocessor for the planned
  PlayStation 3 console.

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REAL TIME PROCESSING

• Real Time Processing
• Most programs on computers run in batch mode.
•       The program starts
•       Reads in input data
•       Processes the information
•       When finished processing writes out
  results
•       Only then can the next program start.

• While one program is running no other program can
  run. However, computer are commonly used to
  process events and signals that must be handled
  in Real Time
• ? an event must be responded to immediately.

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EXAMPLE

• A real time process is a serial communications
  link between two computers.
• Consider a 9600 bps serial link with 8 bit data.
•  

• Serial communications hardware converts the
  serial data to parallel and writes a data byte to
  a Rx register every 0.104 ms.

• But if the CPU does not read each byte before the
  next byte arrives...

.it will lose the information.
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INTERRUPTS

• If CPU is doing nothing else but waiting for this
  data this will work fine, but very wasteful as
  99 of the time doing nothing.

• Cannot easily run other programs as it must be
  sure to check the Rx register every 0.104 ms.

• Not easy to break down a program into 0.1 ms
  chunks, if there are multiple real time
  processes. Becomes more difficult. 

• Such a procedure which checks the status of
  devices or peripherals is known as Polling.

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INTERRUPTS

• An interrupt is a hardware signal that the CPU
  receives from a device to tell it that there is
  new data or a new event that must be responded to
  immediately.
•  
• The CPU handles the interrupt the following way.

• Completes the current instruction and increments
  the PC.
• Saves the PC to the stack and loads the PC with
  the location of the interrupt vector.
• Continues execution at the interrupt vector
  location. This is usually a JUMP to an Interrupt
  Service Routine (ISR)
• ISR completes it task and finishes with a Return
  from Interrupt (RTI)
• The saved value of the PC is popped from the
  stack and the program continues from where it was
  interrupted

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General Purpose Architecture
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Interrupt Service Rountine (ISR)

• The ISR must perform the following tasks.
•  
• First it must save the CPU status register and
  any registers it intends to use.
• Then it services the interrupt
• read the Rx register and saves it in a buffer.
• It must also clear the interrupt condition.
• It restores the CPU status register and any
  registers it has modified and then executes the
  RTI.
•  
• Remember that an interrupt can occur anywhere in
  a program at any time.
• The ISR must not do anything that will affect the
  proper execution of the program. 

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MULTIPLE INTERRUPT SOURCES

• Normally there are many different possible
  sources of interrupt.
• Some of these may be more critical than others.
• High Speed A/D or D/A (very important)
• 50 kHz interrupt occurs every 20 ms
• Serial Port (important)
• 9600 bps an interrupt occurs every 1 ms
• Keyboard (not too important)
• 30 keys/s an interrupt occurs every 33 ms

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INTERRUPT POLLING

•  
• One solution to many interrupts is Software
  Polling.

• All the devices interrupt request lines are ORed
  together and each causes the same interrupt line
  to become active.
• ISR must then poll each device to see which
  caused the interrupt.

This has the disadvantage of being slow.
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VECTORED INTERRUPTS

• A faster solution is to use a Vectored Interrupt.
  
• The 80XXX family, 68000 etc. all use this
  approach.

• Here approach the place in memory that holds the
  address of the service routine for the particular
  device or peripheral that generated the interrupt
  is read into the CPU by the interrupting device
  itself.
• In effect the interrupting device tells the CPU
  who did it and does not wait to be asked.

• This is the fastest possible interrupt servicing
  as no time is wasted polling status bits

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INTERRUPT PRIORITISING

• Consider a high speed A/D at 50 kHz generating an
  interrupt every 20 ms and a lower speed interrupt
  that occurs every 1 ms but takes 30 ms to handle.
  
• The A/D interrupt must interrupt the lower speed
  interrupt or data will be lost.
•  

• A problem that arises is how to handle an
  interrupt that occurs while another is being
  processed?

? Do you interrupt the interrupt.
The ideal solution is to prioritise the
interrupts in hardware.
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INTERRUPTS

• Each interrupt is assigned an Interrupt Priority
  Level, a range 0 - 3.
• Have a interrupt priority register programmed in
  software.
• Interrupt of higher priority can interrupt
  interrupt of lower priority.
• If a lower priority occurs while a high priority
  interrupt occurs it must wait until the interrupt
  is finished.
• The hardware handles the priority.
• The priority structure is highly application
  dependent and no preferred structure exists.
•  
• The mechanical response time associated with
  many physical devices usually are so much greater
  then processor timings that such devices do not
  need instant servicing
• ? requests are assigned a lower priority
•  

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Mask Bit

• Finally each interrupt has a Mask Bit.
•       if the bit is set ? the interrupt is
  masked and if one occurs, then it is ignored.
•       if the bit is cleared ? the interrupt is
  responded to.
•  
• If there are a large number of interrupt sources
• they will usually be handled by grouping a number
  of interrupts to the same interrupt vector and
  use software polling within the group.
•    This works well if the interrupts are related
  and of similar priority, then one ISR can
  efficiently handle them.

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NON-MASKABLE INTERRUPTS

• The Reset line of a CPU can be thought of as a
  Non-Maskable Interrupt (NMI).
• This interrupt is of the highest priority and
  cannot be masked.
• The program never returns to the program that was
  interrupted, as the Reset initialises the PC, all
  internal registers and clears the accumulator.
•  
• Another NMI which is more prevalent nowadays with
  notebook computers than previously is the
  power-fail interrupt.
• This is used with microprocessors in which the
  power supply may fail.
• This is utilised with a voltage sensor that
  detects a voltage drop in the supply voltage.

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OTHER INTERRUPT SOURCES

• As well as external interrupt sources, also
  internal interrupt sources.
• Because interrupts are a good way to handle
  asynchronous events
• ? they are also used to handle some internal CPU
  events.
•  
•  Illegal Instruction Fault
• When the CPU encounter an illegal instruction it
  cannot decode it.
• ? it could crash or it could ignore it,
• neither are good solutions.
•  
• Usually an Illegal Instruction interrupt is
  generated.
• allows software to respond, i.e. to gracefully
  crash or stop program while saving the state of
  CPU to help identify cause of problem.
•   
• Arithmetic Fault
• An arithmetic fault, e.g. divide by zero or
  overflow handled also.
•    Rather than ignore problem an Arithmetic
  Error interrupt is called.

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SOFTWARE INTERRUPT (SWI)

• Frequently an operating system will use a group
  of routines known as Software Interrupts.
•  
• These routines are used by programs to allow the
  operating system to access system resources,
• video access, file access, keyboard access.
• Processor supports these by using a SWI
  instruction followed by an integer, this then
  calls a particular software interrupt.
• Block of memory set aside that contains software
  interrupt vectors.
• This method allows the routines to be rewritten
  and updated and still be compatible with previous
  software.
•  
• Though these routines are really subroutines the
  processor handles them in a similar way to
  interrupts.

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Real-Time Performance

• Hardware Architecture Design changes
• Software Design changes
• H/w and S/w combined approach