Programmable Circuit Fabrics

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Programmable Circuit Fabrics

Zvi Or-Bach President and CEO
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Is Standard Cell on Life Support ?!

• Full Custom technology used to dominate IC design
  until it became too expensive and too lengthy
• Standard Cell technology now dominates IC design
• Is Standard Cell becoming too expensive and too
  lengthy as well ?

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What Caused the Sickness ?

• The Standard Cell basic building blocks -
  inverter, NAND, NOR, etc - are too primitive for
  multi-million gate era
• Exploding Cost of IC Mask-Set
• Lengthy Design Cycle
• Harder to Harvest Performance Improvement of
  Reduced Feature Size

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Exploding Cost of IC Mask-Set
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ASIC Market Crisis at 0.13µ
Mask-set cost 1M ? NRE gt 3M ?
Justifying production value gt 10M
Less than 1000 ASIC designs out of current 10,000
could justify full mask-set cost at 0.13µ
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Lengthy Design Cycle

• Design productivity gap
• Growing gate count and difficult to integrate IP
• Deep sub-micron effects cross talk, power
  integrity..
• Design Convergence
• Routing dominates delay
• Clock skew hard to control
• Debug
• Impossible to probe
• Impossible to FIB

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Harder to Harvest Performance Improvement of
Reduced Feature Size

• Intrinsic delays became smaller than Routing
  delays for most designs
• Hard to implement extra gate shrink (Numerical
  0.07 gate on 0.13 process)

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The Cure

• Coarse Granularity, Repetitive Cell
• - Programmable Cell with mask customizable
  routing fabric
• 97 reduction in customization cost
• Simplified Design Flow
• Good match to ride the technology curve

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97 reduction in customization cost

• Single Custom Mask lt50K
• Logic is programmed by bit-stream
• Routing uses segmented routing and single custom
  via mask

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Generic Fabric Simplifies the Design flow

• Pre-designed logic fabric
• Built-in power distribution
• Built-in full Scan-Chain
• Built-in Clock tree
• 12-20 gates Cell with very high drive
• Intrinsic delays dominate total delay
• Easy to debug
• Built in Scan-Chain provide virtual probe
• Re-programmability provide virtual FIB more

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Good match to ride the technology curve

• Intrinsic delays of 3-4 levels of logic are
  consolidated into the Cell
• Easy to implement extra gate shrink (0.07 micron
  gate) since it is only required for the one
  repetitive cell.

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Coarse Granularity Repetitive Cell - Example

• Detailed implementation of a Programmable Cell
  Fabric with mask customizable routing fabric -
  eASIC
• eASIC technology features
• eASIC implemented with phase shift
• eASIC vs. alternative solutions

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Mask vs. PIC
? Mask customized interconnect Size 2PxP
2P² _at_ 0.18 µ P 0.56 µ Size S 1.2 x 0.56 µ
² ? RAM programmable interconnect 4x RAM Cell
4 Transistor _at_ 0.18 µ 5 RAM Cell 5 x 5.6 µ
² Size 45 S
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eASIC Architecture

• SRAM Look-Up-Table with flip flop
• similar to FPGA
• Metal interconnection between the cells
• standard ASIC routing
• Built-in clock tree
• Built-in scan chain

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eASIC - Universal Fabric

• Configurable by single via mask as
• Logic - Configured by via mask Bit-Stream
• PLD - Programmed by Bit-Stream
• SRAM - Configured by via mask

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eCell 0.13µ
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eCell Layout
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Via Configurable Fabric (M6, M7)
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Typical ePLA implementation
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eUnit

• 16x16 eCELLs
• Memory Interface
• for User Configuration
• for Programming
• 20 Tracks/Cell/Layer
• Clocks Test

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eUNIT Configuration
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eUNIT Clocks

• Clock Grid
• to minimize
• Clock skew

eUnit Clocks
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eASIC Test

• Load eCells-gtXORs
• Nand for tied inputs
• Use all FFs
• Run ATPG
• Reload as Needed
• Reduces the number of tests needed

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eASIC Debug

• Scan all FFs
• create stuck I/O
• cut a line
• change a function
• add a debug line
• prewired
• use during debug

New Function
In the Proto/Production Chips
Debug signal
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Debugging with eASIC - step 2

• Inside Logic Cone
• identify feeding sub-cones (differently colored)

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eASIC vs. Standard Cell - Performance
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eASIC vs. Standard Cell - Density
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eASICs Product Features

• High Density - about 50 of Standard Cell, 25X
  denser than FPGA
• High Performance - similar to Standard Cell, 5X
  higher than FPGA
• power Consumption - similar to Standard Cell,
  1/25 of FPGAs
• Very low NRE Cost
• Shortened Development Cycle
• Ease-of-design
• standard ASIC design flow
• built-in clock-tree, scan-chain, power
  distribution
• easy debug

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eASICs Product Features-with Numerical 0.07µ
gate

• High Density - Similar to Standard Cell (trading
  speed for density)
• High Performance - higher than Standard Cell
• power Consumption - similar to Standard Cell
• Very low NRE Cost
• Shortened Development Cycle
• Ease-of-design
• standard ASIC design flow
• built-in clock-tree, scan-chain, power
  distribution
• easy debug

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Summary

• FPGA fits low volume application
• Full Custom and Standard Cell fit high-end
  high-volume applications
• Programmable Circuit Fabrics are positioned to
  become the dominant IC design technology

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Production Benefits

• eASIC provide about 20 cost reduction due to
  testing
• eASIC provide about 20 cost reduction due to
  yield enhancement
• eASIC wafers serve multi project and would
  commence higher volume and therefore reduce cost
• eASIC wafers are multi use and therefore
  represent lower inventory cost

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Via Configurable Fabric (M7, M8)
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CAE Tools

• Front-End - Simulation and Synthesis
• Verilog
• Synopsys DC, Synplicity
• for IC Designers
• Back-End - Place and Route
• Cadence Monterey Design (LEF, DEF)
• Proprietary Via Router
• eASIC Utilities
• Packing and Mapping Through Bit-Stream and GDS
  II
• PLD, Dual-Port SRAM Macros
• Post Silicon Debugger

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HDL Entry to eASIC/eTool
eASICscripts
User Design(RTL)
eASIC lib
eASICDesignWare
eASIC sim. lib
e-netlist(verilog)
to eTool
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Post Routing Processing in eTool
eASICscripts
FinalDEF
DEF withrouting
eTool
eASIC LEF
eASICfloorplan(DEF)


Verilognetlist
IntrinsicSDF
Scannetlist
SPICEnetlist
GDSII
To chipprogramming
To ATPG
to LVS
To timing simulation
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eASICore

• 4x2 array of eUNITs
• 25K gates

• Test Clocks
• serial programming